Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.

Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.

Abstract: A controlling method for a wireless communication device is provided. The controlling method for the wireless communication device includes: attaching a first Universal Subscriber Identity Module (USIM) to a Long-Term Evolution (LTE) network; determining whether a second USIM is camped on the LTE network; detecting whether a paging collision is happened, if the second USIM is camped on the LTE network; generating a requested International Mobile Subscriber Identity (IMSI) offset for the second USIM, if the paging collision is happened, wherein the requested IMSI offset is 1 or min(T, nB)?1, T is a default paging period and nB is a number of paging occurrences within the default paging period; transmitting an attach request with the requested IMSI offset to the LTE network for the second USIM; receiving a negotiated IMSI offset from the LTE network; and attaching the second USIM to the LTE network with the negotiated IMSI offset.

Abstract: An electronic device including a protective substrate is provided. The protective substrate includes a substrate and an anti-reflection layer. The anti-reflection layer is disposed on the substrate. The anti-reflection layer includes a first sublayer to an nth sublayer sequentially arranged on the substrate, where n is greater than 1, and a product range of a thickness and a refractive index of the nth sublayer ranges from 100 nm to 170 nm.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.

Abstract: A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.

Abstract: A gate structure includes a metal layer, a barrier layer, and a work function layer. The barrier layer covers a bottom surface and sidewalls of the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure. The work function layer surrounds the barrier layer.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: A method for a parallelism-aware wavelength-routed optical networks-on-chip design is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing a WRONoC netlist, design specs and design rules; performing a network construction such that potential positions of each core of a plurality of cores, a plurality of waveguides and a plurality of microring resonators (MRRs) are determined to create a topology; performing a message routing to minimize MRR type usage of the MRRs in the topology; and performing a MRR radius selection to select a radius from MRR-radius options for each MRR type in said topology based on a simulated annealing.

Abstract: Apparatuses and techniques include a substrate, a controller die mounted on the substrate, fingers electrically connecting the controller die to the substrate, a spacer mounted on the substrate adjacent to the controller die, and a first memory die mounted on the spacer. The first memory die is attached to a top surface of the spacer. The spacer has a curved edge facing the controller. The curved edge may have a first curve including a first curve apex extending away from the controller, a first curve peak on one side of the first curve apex, and a second curve peak on an opposite side of the first curve apex than the first curve peak. Additional fingers connect the controller and the first memory die at a point that is aligned with the space between the first curve and a line extending from the first curve peak and the second curve peak.

Abstract: Apparatuses and techniques include a substrate, a controller die mounted on the substrate, fingers electrically connecting the controller die to the substrate, a spacer mounted on the substrate adjacent to the controller die, and a first memory die mounted on the spacer. The first memory die is attached to a top surface of the spacer. The spacer has a curved edge facing the controller. The curved edge may have a first curve including a first curve apex extending away from the controller, a first curve peak on one side of the first curve apex, and a second curve peak on an opposite side of the first curve apex than the first curve peak. Additional fingers connect the controller and the first memory die at a point that is aligned with the space between the first curve and a line extending from the first curve peak and the second curve peak.

Abstract: An RGB format adjustment method includes: obtaining subpixel values having interleaved positions from four pixels in unadjusted RGB format; obtaining subpixel values of a first pixel in an adjusted RGB format according to the obtained subpixel values, wherein the R subpixel value of the adjusted first pixel is equal to an R subpixel value of the unadjusted first pixel, the G subpixel value of the adjusted first pixel is equal to an R subpixel value of a fourth pixel in the unadjusted RGB format, and the B subpixel value of the adjusted first pixel is equal to a B subpixel value of the unadjusted first pixel; and obtaining R subpixel values, G subpixel values and B subpixel values of a second pixel, a third pixel and the fourth pixel according to the obtained subpixel values and the obtained R, G and B subpixel values of the adjusted first pixel.

Abstract: An RGB format adjustment method includes: obtaining subpixel values having interleaved positions from four pixels in unadjusted RGB format; obtaining subpixel values of a first pixel in an adjusted RGB format according to the obtained subpixel values, wherein the R subpixel value of the adjusted first pixel is equal to an R subpixel value of the unadjusted first pixel, the G subpixel value of the adjusted first pixel is equal to an R subpixel value of a fourth pixel in the unadjusted RGB format, and the B subpixel value of the adjusted first pixel is equal to a B subpixel value of the unadjusted first pixel; and obtaining R subpixel values, G subpixel values and B subpixel values of a second pixel, a third pixel and the fourth pixel according to the obtained subpixel values and the obtained R, G and B subpixel values of the adjusted first pixel.

Abstract: AC motor driving system and driving method thereof are provided. The driving system and method are capable of increasing power factor, adjusting waveform of the DC ripple voltage for increasing driving efficiency. The driving system is basically constructed by connecting three circuits. The first circuit is a three-phase full wave rectifying circuit and is used to transfer commercial electricity to a first DC voltage. Then, the second circuit is used to transfer the first DC voltage to a second DC voltage that ripples voltage thereof having a semi-sinusoidal waveform. The third circuit is an AC driving circuit, and receives the second AC voltage for driving the AC motor. Thereby, the driving efficiency can be increased. The capacitance used in the present disclosure has low capacitance value, thus the power factor can be increased, and usage time of the AC motor driving apparatus can also be increased.

Abstract: A light-emitting diode driver includes a power switch, a logic unit and a pulse adjustment signal generator. The power switch is used to control a charging level of a light-emitting diode voltage terminal, and controlled to be turned on or off by a pulse-width modulation signal. The logic unit is coupled to a control terminal of the power switch, and used to generate a frequency control signal. The pulse adjustment signal generator is coupled to the logic unit, and used to generate an operational wave according to the frequency control signal and update the pulse-width modulation signal according to the operational wave. When the duty cycle of the pulse-width modulation signal is smaller than a pulse-width modulation threshold, the operational wave has a first frequency. When the duty cycle of the pulse-width modulation signal is larger than the pulse-width modulation threshold, the operational wave has a second frequency higher than the first frequency.

Abstract: AC motor driving system and driving method thereof are provided. The driving system and method are capable of increasing power factor, adjusting waveform of the DC ripple voltage for increasing driving efficiency. The driving system is basically constructed by connecting three circuits. The first circuit is a three-phase full wave rectifying circuit and is used to transfer commercial electricity to a first DC voltage. Then, the second circuit is used to transfer the first DC voltage to a second DC voltage that ripples voltage thereof having a semi-sinusoidal waveform. The third circuit is an AC driving circuit, and receives the second AC voltage for driving the AC motor. Thereby, the driving efficiency can be increased. The capacitance used in the present disclosure has low capacitance value, thus the power factor can be increased, and usage time of the AC motor driving apparatus can also be increased.