Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.

Abstract: An electronic device is configured to execute instructions: compiling a first AI model and second AI model(s) to a first compiled file and second compiled file(s), respectively, wherein the first compiled file comprises a first data set and a first command set, and the second compiled file(s) comprises second data set(s) and second command set(s); generating light version file(s) for the AI model(s), wherein the light version file(s) comprises the second command set(s) and data patch(es); storing the first compiled file and the light version file(s) to a storage device; loading the first compiled file from the storage device to a memory; loading the light version file(s) from the storage device to the memory; generating the second data set(s) according to the first data set and the data patch(es); and executing the second AI model(s) according to the generated second data set(s) and the second command set(s) in the memory.

Abstract: An optical lens system includes six lens elements from an object side to an image side, the six lens elements are, in order from the object side to the image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. Each of the six lens elements has an object-side surface towards the object side and an image-side surface towards the image side. The image-side surface of the second lens element is concave in a paraxial region thereof. The third lens element has positive refractive power. The image-side surface of the fourth lens element is concave in a paraxial region thereof. The image-side surface of the sixth lens element includes at least one inflection point.

Abstract: A semiconductor structure is provided in the present invention, including a substrate, a deep N-well formed in the substrate, a first well formed in the deep N-well, a first gate formed on the first well, a first source and a first drain formed respectively at two sides of the first gate in the first well, a first doped region formed in the first well, and a metal interconnect electrically connected with the first source and the first doped region, wherein an area of the deep N-well multiplied by a first parameter is a first factor, an area of the first gate multiplied by a second parameter is a second factor, and an area of the metal interconnect divided by a sum of the first factor and the second factor is less than a specification value.

Abstract: A method for a parallelism-aware wavelength-routed optical networks-on-chip design is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing a WRONoC netlist, design specs and design rules; performing a network construction such that potential positions of each core of a plurality of cores, a plurality of waveguides and a plurality of microring resonators (MRRs) are determined to create a topology; performing a message routing to minimize MRR type usage of the MRRs in the topology; and performing a MRR radius selection to select a radius from MRR-radius options for each MRR type in said topology based on a simulated annealing.

Abstract: A method for a parallelism-aware wavelength-routed optical networks-on-chip design is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing a WRONoC netlist, design specs and design rules; performing a network construction such that potential positions of each core of a plurality of cores, a plurality of waveguides and a plurality of microring resonators (MRRs) are determined to create a topology; performing a message routing to minimize MRR type usage of the MRRs in the topology; and performing a MRR radius selection to select a radius from MRR-radius options for each MRR type in said topology based on a simulated annealing.

Abstract: Apparatuses and techniques include a substrate, a controller die mounted on the substrate, fingers electrically connecting the controller die to the substrate, a spacer mounted on the substrate adjacent to the controller die, and a first memory die mounted on the spacer. The first memory die is attached to a top surface of the spacer. The spacer has a curved edge facing the controller. The curved edge may have a first curve including a first curve apex extending away from the controller, a first curve peak on one side of the first curve apex, and a second curve peak on an opposite side of the first curve apex than the first curve peak. Additional fingers connect the controller and the first memory die at a point that is aligned with the space between the first curve and a line extending from the first curve peak and the second curve peak.

Abstract: Apparatuses and techniques include a substrate, a controller die mounted on the substrate, fingers electrically connecting the controller die to the substrate, a spacer mounted on the substrate adjacent to the controller die, and a first memory die mounted on the spacer. The first memory die is attached to a top surface of the spacer. The spacer has a curved edge facing the controller. The curved edge may have a first curve including a first curve apex extending away from the controller, a first curve peak on one side of the first curve apex, and a second curve peak on an opposite side of the first curve apex than the first curve peak. Additional fingers connect the controller and the first memory die at a point that is aligned with the space between the first curve and a line extending from the first curve peak and the second curve peak.

Abstract: An RGB format adjustment method includes: obtaining subpixel values having interleaved positions from four pixels in unadjusted RGB format; obtaining subpixel values of a first pixel in an adjusted RGB format according to the obtained subpixel values, wherein the R subpixel value of the adjusted first pixel is equal to an R subpixel value of the unadjusted first pixel, the G subpixel value of the adjusted first pixel is equal to an R subpixel value of a fourth pixel in the unadjusted RGB format, and the B subpixel value of the adjusted first pixel is equal to a B subpixel value of the unadjusted first pixel; and obtaining R subpixel values, G subpixel values and B subpixel values of a second pixel, a third pixel and the fourth pixel according to the obtained subpixel values and the obtained R, G and B subpixel values of the adjusted first pixel.

Abstract: An RGB format adjustment method includes: obtaining subpixel values having interleaved positions from four pixels in unadjusted RGB format; obtaining subpixel values of a first pixel in an adjusted RGB format according to the obtained subpixel values, wherein the R subpixel value of the adjusted first pixel is equal to an R subpixel value of the unadjusted first pixel, the G subpixel value of the adjusted first pixel is equal to an R subpixel value of a fourth pixel in the unadjusted RGB format, and the B subpixel value of the adjusted first pixel is equal to a B subpixel value of the unadjusted first pixel; and obtaining R subpixel values, G subpixel values and B subpixel values of a second pixel, a third pixel and the fourth pixel according to the obtained subpixel values and the obtained R, G and B subpixel values of the adjusted first pixel.

Abstract: AC motor driving system and driving method thereof are provided. The driving system and method are capable of increasing power factor, adjusting waveform of the DC ripple voltage for increasing driving efficiency. The driving system is basically constructed by connecting three circuits. The first circuit is a three-phase full wave rectifying circuit and is used to transfer commercial electricity to a first DC voltage. Then, the second circuit is used to transfer the first DC voltage to a second DC voltage that ripples voltage thereof having a semi-sinusoidal waveform. The third circuit is an AC driving circuit, and receives the second AC voltage for driving the AC motor. Thereby, the driving efficiency can be increased. The capacitance used in the present disclosure has low capacitance value, thus the power factor can be increased, and usage time of the AC motor driving apparatus can also be increased.

Abstract: A light-emitting diode driver includes a power switch, a logic unit and a pulse adjustment signal generator. The power switch is used to control a charging level of a light-emitting diode voltage terminal, and controlled to be turned on or off by a pulse-width modulation signal. The logic unit is coupled to a control terminal of the power switch, and used to generate a frequency control signal. The pulse adjustment signal generator is coupled to the logic unit, and used to generate an operational wave according to the frequency control signal and update the pulse-width modulation signal according to the operational wave. When the duty cycle of the pulse-width modulation signal is smaller than a pulse-width modulation threshold, the operational wave has a first frequency. When the duty cycle of the pulse-width modulation signal is larger than the pulse-width modulation threshold, the operational wave has a second frequency higher than the first frequency.

Abstract: AC motor driving system and driving method thereof are provided. The driving system and method are capable of increasing power factor, adjusting waveform of the DC ripple voltage for increasing driving efficiency. The driving system is basically constructed by connecting three circuits. The first circuit is a three-phase full wave rectifying circuit and is used to transfer commercial electricity to a first DC voltage. Then, the second circuit is used to transfer the first DC voltage to a second DC voltage that ripples voltage thereof having a semi-sinusoidal waveform. The third circuit is an AC driving circuit, and receives the second AC voltage for driving the AC motor. Thereby, the driving efficiency can be increased. The capacitance used in the present disclosure has low capacitance value, thus the power factor can be increased, and usage time of the AC motor driving apparatus can also be increased.

Abstract: A light-emitting diode driver includes a power switch, a logic unit and a pulse adjustment signal generator. The power switch is used to control a charging level of a light-emitting diode voltage terminal, and controlled to be turned on or off by a pulse-width modulation signal. The logic unit is coupled to a control terminal of the power switch, and used to generate a frequency control signal. The pulse adjustment signal generator is coupled to the logic unit, and used to generate an operational wave according to the frequency control signal and update the pulse-width modulation signal according to the operational wave. When the duty cycle of the pulse-width modulation signal is smaller than a pulse-width modulation threshold, the operational wave has a first frequency. When the duty cycle of the pulse-width modulation signal is larger than the pulse-width modulation threshold, the operational wave has a second frequency higher than the first frequency.

Abstract: A semiconductor package is proposed, in which a substrate is formed with a chip bonding area and a plurality of bond fingers surrounding the chip bonding area, and a plurality of bridging elements are disposed in a stagger manner between the chip bonding area and the bond fingers on the substrate. Multiple wire bonding processes are performed to bond first gold wires between the chip and the bridging elements, and bond second gold wires between the bridging elements and the bond fingers. This therefore significantly shortens a wire bonding distance as compared with only one time of wire bonding for electrically connecting the chip to the substrate. As a result, wire bond operability is improved, and the shortened wire bonding distance reduces wire length so as to enhance resistance of the gold wires to mold flow impact during molding, thereby preventing wire sweeping or wire sagging from occurrence.