Patents by Inventor Kuan-Cheng Liu

Kuan-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098482
    Abstract: A semiconductor structure includes a substrate, at least one first conductive structure, at least one second conductive structure, at least one first memory structure, and at least one second memory structure. The substrate has an array region and a dummy region. The first conductive structure is disposed on the array region. The second conductive structure is disposed on the dummy region. The first memory structure is disposed on the first conductive structure. The first memory structure includes a first channel layer, and the first channel layer is in contact with the first conductive structure. The second memory structure is disposed on the second conductive structure. The second memory structure includes a second channel layer, and the second channel layer is isolated from the second conductive structure.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Kuan-Cheng LIU, Cheng-Wei LIN, Kuang-Wen LIU
  • Patent number: 10103166
    Abstract: A semiconductor device includes a semiconductor substrate, a circuit unit and an align mark. The circuit unit is disposed on the semiconductor substrate. The align mark includes a first part and a second part respectively formed in the semiconductor substrate and adjacent to two opposite sides of the circuit unit, wherein the first part and the second part depart from each other for a predetermined distance along with a first direction.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: October 16, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuan-Cheng Liu, Yu-Lin Liu, Cheng-Wei Lin, Chin-Cheng Yang, Shou-Wei Huang
  • Publication number: 20180294276
    Abstract: A semiconductor device includes a semiconductor substrate, a circuit unit and an align mark. The circuit unit is disposed on the semiconductor substrate. The align mark includes a first part and a second part respectively formed in the semiconductor substrate and adjacent to two opposite sides of the circuit unit, wherein the first part and the second part depart from each other for a predetermined distance along with a first direction.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Kuan-Cheng Liu, Yu-Lin Liu, Cheng-Wei Lin, Chin-Cheng Yang, Shou-Wei Huang
  • Publication number: 20120186852
    Abstract: Disclosed is a structure of electrolessly palladium (Pd) and gold (Au) plated films on a bonding pad, comprising a Pd plated layer on the bonding pad; and an Au plated layer on the Pd plated layer. Also disclosed is an assembled structure formed of the electrolessly Pd—Au plated films wire-bonded with a copper (Cu) or Pd—Cu wire to the Au plated layer. In addition, a process for producing the structure of the electrolessly Pd—Au plated films and an assembling process for the assembled structure are disclosed. According to the present invention, the Pd plated layer is used to replace the conventional nickel layer so as to enhance the wire-bonding strength between the Cu or Pd—Cu wire and the bonding pad.
    Type: Application
    Filed: December 15, 2011
    Publication date: July 26, 2012
    Applicant: Taiwan Uyemura Co., Ltd.
    Inventors: Ming-Hung Lin, Tasi-Tung Kuo, Kuan-Cheng Liu, Ying-Chien Lee, Kuo-Pin Chiu