Patents by Inventor Kuan-Chi Tsai
Kuan-Chi Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11834332Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.Type: GrantFiled: February 14, 2022Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
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Publication number: 20230382723Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Kang-Yi Lien, I-Hsuan Chiu, Yi-Chieh Huang, Chia-Ming Hung, Kuan-Chi Tsai, Hsiang-Fu Chen
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Publication number: 20230278073Abstract: A semiconductor device and method of manufacturing the same that utilizes dielectric pedestals on a sensing electrode. The semiconductor device includes a one or more membranes and an integrated circuit substrate. The integrated circuit substrate includes one or more conductive components disposed within a first dielectric layer on the substrate, with the conductive components interconnected with respective integrated circuit components. The substrate further includes one or more sensing electrodes electrically coupled to the conductive components, and one or more dielectric pedestals positioned within a landing area of the sensing electrode. In addition, the semiconductor device includes at least one cavity that is formed by the membrane positioned over the sensing electrode.Type: ApplicationFiled: March 7, 2022Publication date: September 7, 2023Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
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Publication number: 20230043571Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.Type: ApplicationFiled: February 14, 2022Publication date: February 9, 2023Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
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Publication number: 20230036136Abstract: A semiconductor device and method of manufacturing the device that includes a capacitive micromachined ultrasonic transducer (CMUT). The CMUT includes an integrated circuit substrate, and a sensing electrode positioned on the integrated substrate. The sensing electrode includes a sidewall that forms a wall of an isolation trench adjacent to the sensing electrode, and is patterned before covering dielectric layers are deposited. After patterning of the sensing electrode, one or more dielectric layers are patterned, with one dielectric layer patterned on the sensing electrode and sidewall, and which has a thickness corresponding to the surface roughness of the sensing electrode. The CMUT further includes a membrane positioned above the sensing electrode forming a cavity therein.Type: ApplicationFiled: February 8, 2022Publication date: February 2, 2023Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Wei-Tung Huang, Hsiang-Fu Chen
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Patent number: 11264378Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.Type: GrantFiled: December 20, 2019Date of Patent: March 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shao-Yu Chen, Chih-Ping Chao, Chun-Hung Chen, Chung-Long Chang, Kuan-Chi Tsai, Wei-Kung Tsai, Hsiang-Chi Chen, Ching-Chung Hsu, Cheng-Chang Hsu, Yi-Sin Wang
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Patent number: 11121098Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.Type: GrantFiled: September 6, 2017Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Yu Cheng, Chih-Ping Chao, Kuan-Chi Tsai, Shih-Shiung Chen, Wei-Kung Tsai
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Patent number: 11121100Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.Type: GrantFiled: October 24, 2019Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Yu Cheng, Chih-Ping Chao, Kuan-Chi Tsai, Shih-Shiung Chen, Wei-Kung Tsai
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Publication number: 20200126976Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.Type: ApplicationFiled: December 20, 2019Publication date: April 23, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shao-Yu CHEN, Chih-Ping CHAO, Chun-Hung CHEN, Chung-Long CHANG, Kuan-Chi TSAI, Wei-Kung TSAI, Hsiang-Chi CHEN, Ching-Chung HSU, Cheng-Chang HSU, Yi-Sin WANG
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Publication number: 20200058608Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.Type: ApplicationFiled: October 24, 2019Publication date: February 20, 2020Inventors: Kuo-Yu Cheng, Chih-Ping Chao, Kuan-Chi Tsai, Shih-Shiung Chen, Wei-Kung Tsai
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Patent number: 10515949Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.Type: GrantFiled: October 17, 2013Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Yu Chen, Chih-Ping Chao, Chun-Hung Chen, Chung-Long Chang, Kuan-Chi Tsai, Wei-Kung Tsai, Hsiang-Chi Chen, Ching-Chung Hsu, Cheng-Chang Hsu, Yi-Sin Wang
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Patent number: 10290576Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer.Type: GrantFiled: January 3, 2018Date of Patent: May 14, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 10153300Abstract: A semiconductor device comprises a substrate and a high-electron-mobility transistor (HEMT). The substrate is formed with a recess. At least a portion of the HEMT is disposed in the recess. A method for manufacturing the semiconductor device is also disclosed. A radio frequency (RF) front-end module that employs the semiconductor device is also disclosed.Type: GrantFiled: February 5, 2016Date of Patent: December 11, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Jun-De Jin, Kuan-Chi Tsai
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Patent number: 10090327Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.Type: GrantFiled: January 17, 2014Date of Patent: October 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Kuo-Yu Cheng, Keng-Yu Chen, Wei-Kung Tsai, Kuan-Chi Tsai, Tsung-Yu Yang, Chung-Long Chang, Chun-Hung Chen, Chih-Ping Chao
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Publication number: 20180145025Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer.Type: ApplicationFiled: January 3, 2018Publication date: May 24, 2018Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20180012850Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.Type: ApplicationFiled: September 6, 2017Publication date: January 11, 2018Inventors: Kuo-Yu Cheng, Chih-Ping Chao, Kuan-Chi Tsai, Shih-Shiung Chen, Wei-Kung Tsai
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Patent number: 9865534Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer, wherein a top surface of the metal structure is level with a top surface of the stress reduction layer.Type: GrantFiled: June 13, 2016Date of Patent: January 9, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 9799557Abstract: In accordance with some embodiments, a semiconductor device is provided. The semiconductor device structure includes a substrate, and the substrate has a device region and an edge region. The semiconductor device structure also includes a silicon layer formed on the substrate and a transistor formed on the silicon layer. The transistor is formed at the device region of the substrate. The semiconductor device structure further includes a metal ring formed in the silicon layer. The metal ring is formed at the edge region of the substrate, and the transistor is surrounded by the metal ring.Type: GrantFiled: January 22, 2014Date of Patent: October 24, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu Cheng, Wei-Kung Tsai, Kuan-Chi Tsai
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Patent number: 9761546Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.Type: GrantFiled: February 23, 2016Date of Patent: September 12, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu Cheng, Chih-Ping Chao, Kuan-Chi Tsai, Shih-Shiung Chen, Wei-Kung Tsai
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Publication number: 20170229480Abstract: A semiconductor device comprises a substrate and a high-electron-mobility transistor (HEMT). The substrate is formed with a recess. At least a portion of the HEMT is disposed in the recess. A method for manufacturing the semiconductor device is also disclosed.Type: ApplicationFiled: February 5, 2016Publication date: August 10, 2017Inventors: Jun-De Jin, KUAN-CHI TSAI