Patents by Inventor Kuan-Chia Chen
Kuan-Chia Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136344Abstract: A display device includes a substrate, at least one light emitting unit bound on the substrate, a transparency controllable unit disposed on the substrate, and an integrated circuit unit overlapped with the substrate. The integrated circuit unit includes a semiconducting structure and a conductive structure overlapped with the semiconducting structure. The integrated circuit unit is electrically connected to the at least one light emitting unit and the transparency controllable unit.Type: ApplicationFiled: September 17, 2023Publication date: April 25, 2024Applicant: InnoLux CorporationInventors: Jia-Yuan CHEN, Yu-Chia HUANG, Tsung-Han TSAI, Kuan-Feng LEE
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Publication number: 20230317459Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.Type: ApplicationFiled: June 8, 2023Publication date: October 5, 2023Inventors: Chun-Hsu Yang, Huei-Wen Hsieh, Nai-Hao Yang, Yu-Cheng Hsiao, Chun-Sheng Chen, Che-Wei Tien, Kuan-Chia Chen
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Publication number: 20230299002Abstract: Various back end of line (BEOL) layer formation techniques described herein enable reduced contact resistance, reduced surface roughness, and/or increased semiconductor device performance for BEOL layers such as interconnects and/or metallization layers.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Inventors: Shu-Cheng CHIN, Chih-Chien CHI, Hsin-Ying PENG, Jau-Jiun HUANG, Ya-Lien LEE, Kuan-Chia CHEN, Chia-Pang KUO, Yao-Min LIU
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Patent number: 11694899Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.Type: GrantFiled: June 9, 2020Date of Patent: July 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Hsu Yang, Chun-Sheng Chen, Nai-Hao Yang, Kuan-Chia Chen, Huei-Wen Hsieh, Yu-Cheng Hsiao, Che-Wei Tien
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Publication number: 20220384255Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Chun-Hsu Yang, Chun-Sheng Chen, Nai-Hao Yang, Kuan-Chia Chen, Huei-Wen Hsieh, Yu-Cheng Hsiao, Che-Wei Tien
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Publication number: 20210217622Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.Type: ApplicationFiled: June 9, 2020Publication date: July 15, 2021Inventors: Chun-Hsu Yang, Chun-Sheng Chen, Nai-Hao Yang, Kuan-Chia Chen, Huei-Wen Hsieh, Yu-Cheng Hsiao, Che-Wei Tien
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Patent number: 11018055Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.Type: GrantFiled: December 20, 2019Date of Patent: May 25, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
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Publication number: 20200144112Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.Type: ApplicationFiled: December 20, 2019Publication date: May 7, 2020Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
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Patent number: 10522399Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.Type: GrantFiled: November 30, 2018Date of Patent: December 31, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
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Patent number: 10438846Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.Type: GrantFiled: January 25, 2018Date of Patent: October 8, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
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Publication number: 20190256392Abstract: A negative hydrogen water fabrication device includes a front-mounted filter assembly and a negative hydrogen ion water-activation device. The front-mounted filter assembly includes three resin filter cores that purify and supplies raw water to the negative hydrogen ion water-activation device in which eight activation filter cores, two nanometer gold/platinum filtered water generators, and an ultra-finning resonator are arranged for dissolving minerals in quantum form and trace elements that are needed for human bodies into water for generating, through application of unique physical characteristics, negative hydrogen potential alkaline water that is also subjected to oscillation dissociation to reduce water molecule clusters thereby providing active energy water having high penetration power and dissolution power for drinking by a user for activating cells of human body, enhancing metabolism and improving body quality.Type: ApplicationFiled: February 22, 2018Publication date: August 22, 2019Inventor: Kuan-Chia Chen
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Publication number: 20190164827Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.Type: ApplicationFiled: November 30, 2018Publication date: May 30, 2019Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
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Publication number: 20190164825Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process.Type: ApplicationFiled: January 25, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nai-Hao YANG, Hung-Wen SU, Kuan-Chia CHEN
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Patent number: 9567668Abstract: Embodiments of a plasma apparatus are provided. The plasma apparatus includes a processing chamber and a wafer chuck disposed in the processing chamber. The plasma apparatus also includes a target element located over the wafer chuck and an electromagnet array located over the target element and having a number of electromagnets. Some of the electromagnets in a magnetic-field zone of the electromagnet array are enabled to generate a magnetic field adjacent to the target element. The magnetic-field zone is moved during a semiconductor manufacturing process.Type: GrantFiled: February 19, 2014Date of Patent: February 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chien Chi, Shing-Chyang Pan, Kuan-Chia Chen, Yao-Jen Chang, Huang-Yi Huang, Ching-Hua Hsieh
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Patent number: 9472449Abstract: A method of fabricating a semiconductor structure includes forming a dielectric layer overlaying a substrate; forming a trench in the dielectric layer; forming a first barrier layer lining the trench; forming a conductive layer overlaying the first barrier layer; forming a second barrier layer overlaying the conductive layer; forming a metallic sacrificial layer to cover the second barrier layer and to fill the trench; and performing a polishing process to remove the materials above a bottom portion of the second barrier layer.Type: GrantFiled: January 15, 2014Date of Patent: October 18, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuan-Chia Chen, Shing-Chyang Pan, Chih-Chien Chi, Ching-Hua Hsieh
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Patent number: 9275894Abstract: In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer on a semiconductor substrate. The dielectric layer has at least one first trench in the dielectric layer. The method also includes forming a seed layer on a sidewall and a bottom surface of the first trench. The method further includes forming a first conductive layer on the seed layer. The method includes performing a thermal treatment process to melt and transform the seed layer and the first conductive layer into a second conductive layer. The method also includes forming a third conductive layer on the second conductive layer to fill the first trench.Type: GrantFiled: January 22, 2014Date of Patent: March 1, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Feng Lin, Kuan-Chia Chen, Ching-Hua Hsieh
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Publication number: 20150235823Abstract: Embodiments of a plasma apparatus are provided. The plasma apparatus includes a processing chamber and a wafer chuck disposed in the processing chamber. The plasma apparatus also includes a target element located over the wafer chuck and an electromagnet array located over the target element and having a number of electromagnets. Some of the electromagnets in a magnetic-field zone of the electromagnet array are enabled to generate a magnetic field adjacent to the target element. The magnetic-field zone is moved during a semiconductor manufacturing process.Type: ApplicationFiled: February 19, 2014Publication date: August 20, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien CHI, Shing-Chyang PAN, Kuan-Chia CHEN, Yao-Jen CHANG, Huang-Yi HUANG, Ching-Hua HSIEH
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Publication number: 20150206791Abstract: In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer on a semiconductor substrate. The dielectric layer has at least one first trench in the dielectric layer. The method also includes forming a seed layer on a sidewall and a bottom surface of the first trench. The method further includes forming a first conductive layer on the seed layer. The method includes performing a thermal treatment process to melt and transform the seed layer and the first conductive layer into a second conductive layer. The method also includes forming a third conductive layer on the second conductive layer to fill the first trench.Type: ApplicationFiled: January 22, 2014Publication date: July 23, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Feng LIN, Kuan-Chia CHEN, Ching-Hua HSIEH
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Publication number: 20150200126Abstract: A method of fabricating a semiconductor structure includes forming a dielectric layer overlaying a substrate; forming a trench in the dielectric layer; forming a first barrier layer lining the trench; forming a conductive layer overlaying the first barrier layer; forming a second barrier layer overlaying the conductive layer; forming a metallic sacrificial layer to cover the second barrier layer and to fill the trench; and performing a polishing process to remove the materials above a bottom portion of the second barrier layer.Type: ApplicationFiled: January 15, 2014Publication date: July 16, 2015Applicant: Taiwan Semiconductor Manufacturing CO., LTD.Inventors: Kuan-Chia Chen, Shing-Chyang Pan, Chih-Chien Chi, Ching-Hua Hsieh