Patents by Inventor Kuan-Chuan Chen
Kuan-Chuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240107087Abstract: The subject application relates to a server, terminal and non-transitory computer-readable medium. The server for handling streaming data for a live streaming, comprising one or a plurality of processors, wherein the one or plurality of processors execute a machine-readable instruction to perform: recording the streaming data for the live streaming; storing the streaming data as archive contents with first identifier; receiving interaction information during the live streaming; storing the interaction information as contexts with second identifier, transmitting the archive contents with first identifier to a first user terminal; and transmitting the contexts to the first user terminal according to the first identifier and the second identifier. According to the subject application, the archive contents may be more immersive and the user experience may be enhanced.Type: ApplicationFiled: June 26, 2023Publication date: March 28, 2024Inventors: Yu-Chuan CHANG, Kun-Ze LI, Che-Wei LIU, Chieh-Min CHEN, Kuan-Hung LIU
-
Publication number: 20240069618Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
-
Patent number: 10535734Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.Type: GrantFiled: July 2, 2019Date of Patent: January 14, 2020Assignee: United Microelectronics Corp.Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
-
Patent number: 10497805Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.Type: GrantFiled: August 14, 2018Date of Patent: December 3, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
-
Publication number: 20190326398Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Applicant: United Microelectronics Corp.Inventors: SHIN-HUNG LI, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
-
Patent number: 10396157Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.Type: GrantFiled: March 6, 2018Date of Patent: August 27, 2019Assignee: United Microelectronics Corp.Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
-
Publication number: 20190245038Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.Type: ApplicationFiled: March 6, 2018Publication date: August 8, 2019Applicant: United Microelectronics Corp.Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
-
Publication number: 20190115469Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.Type: ApplicationFiled: August 14, 2018Publication date: April 18, 2019Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
-
Patent number: 10084083Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.Type: GrantFiled: October 17, 2017Date of Patent: September 25, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
-
Patent number: 9972539Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.Type: GrantFiled: March 30, 2017Date of Patent: May 15, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
-
Patent number: 9716139Abstract: A method for forming a high voltage transistor is provided. First, a substrate having a top surface is provided, following by forming a thermal oxide layer on the substrate. At least a part of the thermal oxidation layer is removed to form a recess in the substrate, wherein a bottom surface of the recess is lower than the top surface of the substrate. A gate oxide layer is formed in the recess, then a gate structure is formed on the gate oxide layer. The method further includes forming a source/drain region in the substrate.Type: GrantFiled: June 2, 2015Date of Patent: July 25, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuan-Chuan Chen, Chih-Chung Wang, Wen-Fang Lee, Nien-Chung Li, Shih-Yin Hsiao
-
Publication number: 20170207127Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.Type: ApplicationFiled: March 30, 2017Publication date: July 20, 2017Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
-
Patent number: 9653460Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.Type: GrantFiled: March 1, 2016Date of Patent: May 16, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
-
Publication number: 20160358919Abstract: A method for forming a high voltage transistor is provided. First, a substrate having a top surface is provided, following by forming a thermal oxide layer on the substrate. At least a part of the thermal oxidation layer is removed to form a recess in the substrate, wherein a bottom surface of the recess is lower than the top surface of the substrate. A gate oxide layer is formed in the recess, then a gate structure is formed on the gate oxide layer. The method further includes forming a source/drain region in the substrate.Type: ApplicationFiled: June 2, 2015Publication date: December 8, 2016Inventors: Kuan-Chuan Chen, Chih-Chung Wang, Wen-Fang Lee, Nien-Chung Li, Shih-Yin Hsiao
-
Patent number: 9484422Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.Type: GrantFiled: October 14, 2015Date of Patent: November 1, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Huang Yu, Shih-Yin Hsiao, Wen-Fang Lee, Shu-Wen Lin, Kuan-Chuan Chen
-
Publication number: 20160043193Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.Type: ApplicationFiled: October 14, 2015Publication date: February 11, 2016Inventors: Kun-Huang Yu, Shih-Yin Hsiao, Wen-Fang Lee, Shu-Wen Lin, Kuan-Chuan Chen
-
Patent number: 9196695Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.Type: GrantFiled: May 8, 2014Date of Patent: November 24, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Huang Yu, Shih-Yin Hsiao, Wen-Fang Lee, Shu-Wen Lin, Kuan-Chuan Chen
-
Publication number: 20150287797Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.Type: ApplicationFiled: May 8, 2014Publication date: October 8, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kun-Huang Yu, Shih-Yin Hsiao, Wen-Fang Lee, Shu-Wen Lin, Kuan-Chuan Chen