Patents by Inventor Kuan Chuang KOAY

Kuan Chuang KOAY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220342434
    Abstract: The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Inventors: Xiaodong MENG, Fan YANG, YuFei PAN, Hua GUAN, Kuan Chuang KOAY, Jize JIANG
  • Publication number: 20220308609
    Abstract: In certain aspects, a system includes an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Inventors: Kuan Chuang KOAY, Hua GUAN, Jize JIANG
  • Patent number: 11409313
    Abstract: Aspects of the present disclosure provide a voltage reference architecture. An example circuit generally includes a resistor ladder, a reference current source, and a plurality of multiplexers. The resistor ladder comprises a plurality of resistive elements coupled in series. The reference current source has an output coupled to the resistor ladder. The plurality of multiplexers have inputs coupled to one or more nodes between the plurality of resistive elements and the output of the reference current source, each of the multiplexers having an output selectively coupled to one of the inputs of the multiplexer.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: August 9, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Jize Jiang, Hua Guan, Kuan Chuang Koay
  • Patent number: 11385667
    Abstract: An LDO regulator is provided that includes a bias circuit that generates a bias current having a non-linear relationship to an output current for the LDO regulator. The LDO regulator is also configured to clamp the output current.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 12, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Kuan Chuang Koay, Hua Guan, YuFei Pan
  • Publication number: 20220206520
    Abstract: Aspects of the present disclosure provide a voltage reference architecture. An example circuit generally includes a resistor ladder, a reference current source, and a plurality of multiplexers. The resistor ladder comprises a plurality of resistive elements coupled in series. The reference current source has an output coupled to the resistor ladder. The plurality of multiplexers have inputs coupled to one or more nodes between the plurality of resistive elements and the output of the reference current source, each of the multiplexers having an output selectively coupled to one of the inputs of the multiplexer.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Inventors: Jize JIANG, Hua GUAN, Kuan Chuang KOAY
  • Publication number: 20200201373
    Abstract: An LDO regulator is provided that includes a bias circuit that generates a bias current having a non-linear relationship to an output current for the LDO regulator. The LDO regulator is also configured to clamp the output current.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 25, 2020
    Inventors: Kuan Chuang KOAY, Hua GUAN, YuFei PAN