Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.

Abstract: A device includes a transistor, a backside via, and a pair of sidewall spacers. The transistor includes a gate structure, a channel layer surrounded by the gate structure, and a first source/drain structure and a second source/drain structure connected to the channel layer. The backside via is under and connected to the first source/drain structure and includes a first portion, a second portion between the first portion and the first source/drain structure, and a third portion tapering from the first portion to the second portion in a cross-sectional view. The pair of sidewall spacers are on opposite sidewalls of the second portion of the backside via but not on opposite sidewalls of the first portion of the backside via.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.

Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.

Abstract: A protecting method for preventing solder crack failure in an electronic product is provided. Firstly, a step (a) is performed to confirm that a crack incidence rate of a metallic solder material in a printed circuit board is high. In a step (b), a protecting mechanism of controlling the electronic product to enter an idle mode and leave the idle mode is activated. Consequently, an operating temperature of the electronic product decreases at a first average drop rate.

Abstract: A method of moving a susceptor in a processing system, suitable for use in semiconductor processing, is provided. The method includes: moving a first susceptor from an interior volume of a first enclosure to an interior volume of a process chamber during a first time period; and positioning, during a second time period, a first substrate on the first susceptor when the first susceptor is in the process chamber, wherein the interior volume of the first enclosure and interior volume of the process chamber are maintained at a non-atmospheric pressure from the beginning of the first time period until the end of the second time period.

Abstract: An electronic device includes a substrate, a first silicon transistor, a second silicon transistor and a first oxide semiconductor transistor. The first silicon transistor, the second silicon transistor and the first oxide semiconductor transistor are disposed on the substrate. The first silicon transistor has a first terminal electrically connected to a first voltage level, a second terminal and a control terminal. The second silicon transistor has a first terminal electrically connected to the second terminal of the first silicon transistor, a second terminal electrically connected to a second voltage level, and a control terminal electrically connected to the control terminal of the first silicon transistor. The first oxide semiconductor transistor has a first terminal electrically connected to the first terminal of the second silicon transistor. Wherein, a voltage value of the first voltage level is greater than a voltage value of the second voltage level.

Abstract: An asymmetric half-bridge converter is provided. The asymmetric half-bridge converter includes a switch circuit, a resonance tank, a current sensor, and a controller. The current sensor senses a waveform of a resonance current flowing through the resonance tank to generate a sensing result. The controller determines the sensing result. When the sensing result indicates that an ending current value of a primary resonance waveform of the resonance current is greater than a predetermined value, the controller performs a first switching operation on the switch circuit. When the sensing result indicates that the ending current value of the primary resonance waveform is less than or equal to the predetermined value, the controller performs a second switching operation on the switch circuit.

Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.

Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.

Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.

Abstract: A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.

Abstract: There is provided a Bluetooth audio system including an audio source and an audio sink. The audio sink responds multiple codec types supported thereby in a protocol message exchange of a first mode, and responds a single codec type only supported thereby and a maximum transmission unit (MTU) size as 367 bytes in a protocol message exchange of a second mode. The audio source reduces a sampling number of the used codec to be lower than 1024 samples after receiving the single codec type and the MTU size of 367 bytes.

Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.

Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.

Abstract: A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.

Abstract: A failure mode detection method is provided. A first default read voltage is changed to a first read retry voltage by a first increment, and a second default read voltage is changed to a second read retry voltage by a second increment. A memory cell array of a solid state storage device is successfully read according to the first and second read retry voltages. If an absolute value of the first increment minus an absolute value of the second increment is larger than a predetermined voltage value, the memory cell array is in a data retention failure mode. If the absolute value of the first increment minus the absolute value of the second increment is smaller than the predetermined voltage value, the memory cell array is in a low temperature write high temperature read failure mode.

Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.

Abstract: A read table management method for a solid state storage device includes the following steps. If the lowest computation value in a hot group is lower than the highest computation value in a cold group when a read table adjusting process is enabled, a first read voltage set corresponding to the lowest computation value in the hot group and a second read voltage set corresponding to the highest computation value in the cold group are swapped with each other. Consequently, the second read voltage set becomes to belong to the hot group, and the first read voltage set becomes to belong to the cold group.