Abstract: Embodiments of the present disclosure provide a protective layer deposited over bottom structures to protect the bottom structure during fabrication of upper structures. The protective layer may prevent STI loss and bottom spacer loss during source/drain etch back process. The protective layer may also improve process uniformity by also eliminate process loading or non-uniformity in the STI loss, fin sidewall spacer height, and recess profiles. The protective layer may also slow down fin sidewall spacer etching rate during semiconductor fin etch back, thus, improving source/drain regions profile control.

Abstract: A semiconductor device includes: a semiconductor fin extending along a first lateral direction; a gate structure extending along a second lateral direction perpendicular to the first lateral direction and straddling the semiconductor fin; an epitaxial structure disposed in the semiconductor fin and next to the gate structure; a first interconnect structure extending along the second lateral direction and disposed above the epitaxial structure; and a dielectric layer including a first portion and a second portion that form a stair.

Abstract: A nucleic acid probe set is disclosed. The nucleic acid probe set comprises a detection probe and a capture probe, and the detection probe and the capture probe both include a nucleotide sequence that is extracted from a conserved region of a genome sequence belong to a BK virus. A nucleic acid lateral flow immunoassay for using in detection of BK virus is also disclosed. The nucleic acid lateral flow immunoassay comprises: the forgoing nucleic acid probe set, a test strip, and a streptavidin (SA) solution. Experimental data have proved that, the nucleic acid lateral flow immunoassay can be adopted for conducting a BK virus detection on a sample that is collected from environmental water, sewage water, drinking water, urine, or serum.

Abstract: A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes forming a patterned hardmask over an underlying target layer on a substrate; and performing plasma fabrication operations in parallel on the patterned hardmask and underlying target layer in a plasma etching chamber using a plasma etch gas and a selective source gas. The plasma operations include forming a protective cap on the patterned hardmask; and removing portions of the underlying layer that are not covered by the patterned hardmask. In various embodiments, the selective source gas includes a chemical compound that includes a halogen gas that can be dissociated into a metal and a halogen, and the plasma operations include dissociating the metal and the halogen in the selective source gas and forming a protective cap on the patterned hardmask using the metal that has been dissociated.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a gate electrode over a substrate. A pair of source/drain regions are disposed in the substrate on opposing sides of the gate electrode. A dielectric layer is over the substrate. An etch stop layer is between the gate electrode and the dielectric layer. A gate capping layer overlies the gate electrode, continuously extends from a top surface of the etch stop layer to a top surface of the gate electrode, and comprises a curved sidewall over the top surface of the etch stop layer. A conductive contact overlies an individual source/drain region. A width of the conductive contact continuously decreases from a top surface of the conductive contact to a first point disposed above a lower surface of the gate capping layer. The conductive contact extends along the curved sidewall of the gate capping layer.

Abstract: In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions. A lower inter-level dielectric (ILD) layer is formed over the pair of source/drain regions and around the gate electrode. A gate capping layer is formed over the gate electrode. A selective etch and deposition process is performed to form a dielectric protection layer on the gate capping layer while forming a contact opening within the lower ILD layer. A lower source/drain contact is formed within the contact opening.

Abstract: A method for manufacturing a semiconductor structure includes forming a semiconductor portion which has an exposed region; forming two fin sidewalls which are disposed at two opposite sides of the exposed region of the semiconductor portion, and which include a dielectric material; and performing an etching process such that the exposed region of the semiconductor portion is etched away to form a recess while a protection layer is formed to protect each of the fin sidewalls during the etching process. Other methods for manufacturing the semiconductor structure are also disclosed.

Abstract: A device includes a first semiconductor structure, a second semiconductor structure, and an isolation structure which is disposed between the first and second semiconductor structures, and which includes a dielectric material having a dielectric constant higher than 8 and lower than 16. A method for manufacturing the device is also disclosed.

Abstract: A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.

Abstract: In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions. A lower inter-level dielectric (ILD) layer is formed over the pair of source/drain regions and around the gate electrode. A gate capping layer is formed over the gate electrode. A selective etch and deposition process is performed to form a dielectric protection layer on the gate capping layer while forming a contact opening within the lower ILD layer. A lower source/drain contact is formed within the contact opening.