Patents by Inventor Kuan Dong

Kuan Dong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250254873
    Abstract: Systems, devices, and methods for fabricating staircase structures in three-dimensional (3D) semiconductor devices are provided. In one aspect, a method includes providing a first deck comprising a first stack of first sacrificial layers and first isolating layers extending along a first direction. At least a part of the first deck is etched to form a first staircase structure. A second deck adjacent to the first deck along a second direction is provided, the second deck comprising a second stack of second sacrificial layers and second isolating layers extending along the first direction, the second sacrificial layers and the second isolating layers alternating with each other along the second direction. At least a part of the second deck is etched to form a second staircase structure. Contact structures extending through at least one of the first staircase structure or the second staircase structure along the second direction are formed.
    Type: Application
    Filed: March 12, 2024
    Publication date: August 7, 2025
    Inventors: Meng XIAO, Kuan DONG, Longdong LIU, Zhou HE, Gang ZHANG
  • Publication number: 20250159883
    Abstract: Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The disclosed semiconductor device can comprise a stack structure comprising alternative conductive layers and dielectric layers, and a gate line structure extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory fingers. The gate line structure can comprise gate line slit structure segments aligned along the first lateral direction, and at least one first dummy contact structure located between adjacent gate line slit structure segments in the first lateral direction.
    Type: Application
    Filed: November 21, 2023
    Publication date: May 15, 2025
    Inventors: Kuan Dong, Meng Xiao, Zhou He, Longdong Liu, Xianghui Zhao, Gang Zhang
  • Publication number: 20250159884
    Abstract: Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. A disclosed semiconductor device comprises a stack structure comprising alternative conductive layers and dielectric layers, and a gate line structure extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory blocks. The gate line structure comprises gate line slit structure segments aligned along the first lateral direction, and at least one dummy channel structure located between the gate line slit structure segments in the first lateral direction.
    Type: Application
    Filed: November 21, 2023
    Publication date: May 15, 2025
    Inventors: Zhou He, Meng Xiao, Longdong Liu, Kuan Dong, Gang Zhang
  • Publication number: 20250159894
    Abstract: Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. One disclosed semiconductor device comprises a stack structure comprising an array region and a contact region, and a gate line slit structure extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory blocks. The gate line slit structure comprises a first dummy channel structure located at a boundary between the array region and the contact region, a first gate line slit segment extending laterally from the first dummy channel structure into the array region, and a second gate line slit segment extending laterally from the first dummy channel structure into the contact region.
    Type: Application
    Filed: November 21, 2023
    Publication date: May 15, 2025
    Inventors: Zhou He, Meng Xiao, Kuan Dong, Longdong Liu, Gang Zhang
  • Publication number: 20250142817
    Abstract: Implementations of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In some implementations, the disclosed 3D memory device comprises: a stack structure including a plurality of dielectric layers and conductive layers alternatively stacked in a vertical direction; an array of channel structures each vertically penetrating the stack structure, each channel structure including a functional layer and a channel layer; and a plurality of isolation structures extending in parallel along a first lateral direction and vertically in an upper portion of the stack structure, each isolation structure being in contact with the channel layers of two adjacent rows of channel structures.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 1, 2025
    Inventors: Kuan Dong, Gang Zhang, Meng Xiao, Longdong Liu, Zhou He, Pan Wang, Jin Dong, Meng Xiao, Liheng Liu
  • Publication number: 20250105149
    Abstract: A semiconductor device includes a stack comprising interleaved conductive layers and dielectric layers stacked along a first direction, and a contact structure extending through the stack along the first direction. The conductive layers include a first conductive layer and a second conductive layer under the first conductive layer, and the first conductive layer is in contact with the contact structure. The first conductive layer includes a first portion having a first thickness and a second portion having a second thickness less than the first thickness in contact with the contact structure.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 27, 2025
    Inventors: Meng Xiao, Kuan Dong, Longdong Liu, Zhou He, Xianghui Zhao, Zuixin Zeng, Gang Zhang