Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.

Abstract: A method of power control can include receiving at a UE a first downlink reference signal from a repeater and a second downlink reference signal from a base station, the first downlink reference signal corresponding to a first path that is between the UE and the base station and passes the repeater, the second downlink reference signal corresponding to a second path that is between the UE and the base station. The UE estimates a first uplink path loss of the first path and a second uplink path loss of the second path and determine a first uplink transmit power corresponding to the first path and a second uplink transmit power corresponding to the second path. The UE performs an uplink transmission on the first path based on the first uplink transmit power and on the second path based on the second uplink transmit power.

Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes at least one first semiconductor element and at least one second semiconductor element over a substrate, a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element, a first work function metal layer wrapping around each of the at least one first semiconductor element and extending continuously from the at least one first semiconductor element to a top surface of the dielectric fin, and a second work function metal layer disposed over the at least one second semiconductor element and the first work function metal layer.

Abstract: A method includes forming an epitaxial source/drain region in a substrate; forming a first inter-layer dielectric over the epitaxial source/drain region; forming a gate stack over the substrate and adjacent to the first inter-layer dielectric; forming a gate mask over the gate stack; forming a source/drain plug through the first inter-layer dielectric and electrically connected to the epitaxial source/drain region; depositing a dielectric layer over the gate mask and the first inter-layer dielectric, the dielectric layer having a different etch selectivity than the gate mask; forming a second inter-layer dielectric over the dielectric layer; etching an opening through the second inter-layer dielectric and the dielectric layer, the opening exposing the source/drain plug and the gate mask; and forming a conductive feature in the opening, the conductive feature being electrically connected to the source/drain plug.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5 d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3 d orbitals.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

Abstract: An image input system and an image input method thereof are disclosed. The system includes an input equipment which includes an image capturing module and a first communication module, and a processing apparatus which includes a second communication module, a calculation module and a conversion module. The image capturing module is configured to capture an image of an object on a display and to detect an image-capturing distance or a position of the object. The captured image, the image-capturing distance or the object position is then communicated to the processing apparatus and may be analyzed by the calculation module to calculate an edge position of the image. The conversion module is configured to convert the edge position, the captured image or the object position to an input signal. This invention creates a new type of human-machine interface through the image capturing module, and the first and second communication modules.