Patents by Inventor Kuan-Hao TSENG
Kuan-Hao TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11933809Abstract: The present application discloses an inertial sensor comprising a proof mass, an anchor, a flexible member and several sensing electrodes. The anchor is positioned on one side of the sensing, mass block in a first axis. The flexible member is connected to the anchor point and extends along the first axis towards the proof mass to connect the proof mass, in which the several sensing electrodes are provided. In this way, the present application can effectively solve the problems of high difficulty in the production and assembly of inertial sensors and poor product reliability thereof.Type: GrantFiled: April 6, 2022Date of Patent: March 19, 2024Assignee: SENSORTEK TECHNOLOGY CORP.Inventors: Shih-Wei Lee, Chia-Hao Lin, Shih-Hsiung Tseng, Kuan-Ju Tseng, Chao-Shiun Wang
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Patent number: 11689188Abstract: The present invention discloses a signal output circuit having anti-interference mechanism. An amplifier is electrically coupled to a power supply and a ground terminal through a first and a second amplifier bond wires, and generates an amplified output signal. A transformer circuit includes a transformer performing impedance transformation on the amplified output signal to generate a transformed output signal and a voltage-stabilizing capacitor suppressing second-order harmonics of the amplifier. A power-terminal side anti-interference circuit includes a power-terminal side bond wire and a power-terminal side anti-interference capacitor. The power-terminal side bond wire is electrically coupled to the ground terminal.Type: GrantFiled: April 29, 2021Date of Patent: June 27, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Kuan-Hao Tseng, Ka-Un Chan, Po-Chih Wang
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Patent number: 11563009Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.Type: GrantFiled: December 28, 2020Date of Patent: January 24, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jenn-Gwo Hwu, Samuel C. Pan, Chien-Shun Liao, Kuan-Hao Tseng
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Publication number: 20210351764Abstract: The present invention discloses a signal output circuit having anti-interference mechanism. An amplifier is electrically coupled to a power supply and a ground terminal through a first and a second amplifier bond wires, and generates an amplified output signal. A transformer circuit includes a transformer performing impedance transformation on the amplified output signal to generate a transformed output signal and a voltage-stabilizing capacitor suppressing second-order harmonics of the amplifier. A power-terminal side anti-interference circuit includes a power-terminal side bond wire and a power-terminal side anti-interference capacitor. The power-terminal side bond wire is electrically coupled to the ground terminal.Type: ApplicationFiled: April 29, 2021Publication date: November 11, 2021Inventors: KUAN-HAO TSENG, KA-UN CHAN, PO-CHIH WANG
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Patent number: 11165516Abstract: An output power linearization method, suitable for a calibration system, includes the following operations: providing an instruction signal, which corresponding to a currently ideal output power among multiple ideal output powers, to an emission module of the calibration system so that the emission module outputs a radio frequency (RF) signal with a practical output power according to the instruction signal; obtaining a feedback signal, by a feedback circuit of the calibration system, from an output terminal of the emission module, and calculating a feedback output power from the feedback signal; calculating an output difference between the currently ideal output power and the feedback output power; if an absolute value of the output difference is larger than an absolute value of a feedback error of the feedback circuit, adjusting a present gain of the emission module so that the practical output power approaches the currently ideal output power.Type: GrantFiled: September 9, 2020Date of Patent: November 2, 2021Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Kuan-Hao Tseng, Ka-Un Chan, Po-Chih Wang
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Publication number: 20210281332Abstract: An output power linearization method, suitable for a calibration system, includes the following operations: providing an instruction signal, which corresponding to a currently ideal output power among multiple ideal output powers, to an emission module of the calibration system so that the emission module outputs a radio frequency (RF) signal with a practical output power according to the instruction signal; obtaining a feedback signal, by a feedback circuit of the calibration system, from an output terminal of the emission module, and calculating a feedback output power from the feedback signal; calculating an output difference between the currently ideal output power and the feedback output power; if an absolute value of the output difference is larger than an absolute value of a feedback error of the feedback circuit, adjusting a present gain of the emission module so that the practical output power approaches the currently ideal output power.Type: ApplicationFiled: September 9, 2020Publication date: September 9, 2021Inventors: Kuan-Hao TSENG, Ka-Un CHAN, Po-Chih WANG
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Publication number: 20210193667Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.Type: ApplicationFiled: December 28, 2020Publication date: June 24, 2021Inventors: Jenn-Gwo HWU, Samuel C. PAN, Chien-Shun LIAO, Kuan-Hao TSENG
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Patent number: 10879249Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.Type: GrantFiled: August 12, 2019Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jenn-Gwo Hwu, Samuel C. Pan, Chien-Shun Liao, Kuan-Hao Tseng
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Patent number: 10707135Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.Type: GrantFiled: November 7, 2017Date of Patent: July 7, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuan-Hao Tseng, Chien-Ting Lin, Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Chueh-Fei Tai, Cheng-Ping Kuo
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Patent number: 10629695Abstract: A semiconductor device includes a metal gate on a substrate, a polysilicon layer on the metal gate, a hard mask on the polysilicon layer, and a source/drain region adjacent to two sides of the metal gate. Preferably, the metal gate includes a ferroelectric (FE) layer on the substrate, a work function metal layer on the FE layer, and a low resistance metal layer on the work function metal layer.Type: GrantFiled: January 4, 2019Date of Patent: April 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Cheng-Ping Kuo, Kuan-Hao Tseng
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Publication number: 20190363089Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102 ?/? to 1.0×1010 ?/?.Type: ApplicationFiled: August 12, 2019Publication date: November 28, 2019Inventors: Jenn-Gwo HWU, Samuel C. PAN, Chien-Shun LIAO, Kuan-Hao TSENG
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Patent number: 10431497Abstract: A manufacturing method of an epitaxial fin-shaped structure includes the following steps. A substrate is provided. A recess is formed in the substrate. An epitaxial layer is formed on the substrate. The epitaxial layer is partly formed in the recess and partly formed outside the recess. The epitaxial layer has a dent formed on the top surface of the epitaxial layer, and the dent is formed corresponding to the recess in a thickness direction of the substrate. A nitride layer is conformally formed on the epitaxial layer. An oxide layer is formed on the nitride layer. A first planarization process is performed to remove a part of the oxide layer, and the first planarization process is stopped on the nitride layer. The epitaxial layer in the recess is patterned for forming at least one epitaxial fin-shaped structure.Type: GrantFiled: April 12, 2018Date of Patent: October 1, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Kuang Hsieh, Kuan-Hao Tseng, Yu-Hsiang Lin, Shih-Hung Tsai, Yu-Ting Tseng
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Publication number: 20190295896Abstract: A manufacturing method of an epitaxial fin-shaped structure includes the following steps. A substrate is provided. A recess is formed in the substrate. An epitaxial layer is formed on the substrate. The epitaxial layer is partly formed in the recess and partly formed outside the recess. The epitaxial layer has a dent formed on the top surface of the epitaxial layer, and the dent is formed corresponding to the recess in a thickness direction of the substrate. A nitride layer is conformally formed on the epitaxial layer. An oxide layer is formed on the nitride layer. A first planarization process is performed to remove a part of the oxide layer, and the first planarization process is stopped on the nitride layer. The epitaxial layer in the recess is patterned for forming at least one epitaxial fin-shaped structure.Type: ApplicationFiled: April 12, 2018Publication date: September 26, 2019Inventors: Po-Kuang Hsieh, Kuan-Hao Tseng, Yu-Hsiang Lin, Shih-Hung Tsai, Yu-Ting Tseng
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Patent number: 10381353Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.Type: GrantFiled: September 28, 2017Date of Patent: August 13, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jenn-Gwo Hwu, Samuel C. Pan, Chien-Shun Liao, Kuan-Hao Tseng
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Publication number: 20190221639Abstract: A method for fabrication a nanosheet device includes providing forming a stacked layer on a substrate, having first material layers and second material layers in different materials, alternatingly stacked up. The stacked layer is patterned to a stacked fin. A dummy stack is formed on the stacked fin. An etching back process is performed with the dummy stack with spacers to etch the stacked fin and expose the substrate. Laterally etches the first material layers and the second material layers, to have indent portions. Inner spacers fill the indent portions. A first/second source/drain layer is formed on the substrate at both sides of the dummy stack. Etching process is performed to remove the dummy gate of the dummy stack and the selected one of the first material layers and the second material layers between the inner spacers. Metal layer fills between the spacers and the inner spacers.Type: ApplicationFiled: January 12, 2018Publication date: July 18, 2019Applicant: United Microelectronics Corp.Inventors: Kuan-Hao Tseng, Yu-Hsiang Lin, Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Chueh-Fei Tai, Cheng-Ping Kuo
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Publication number: 20190140068Abstract: A semiconductor device includes a metal gate on a substrate, a polysilicon layer on the metal gate, a hard mask on the polysilicon layer, and a source/drain region adjacent to two sides of the metal gate. Preferably, the metal gate includes a ferroelectric (FE) layer on the substrate, a work function metal layer on the FE layer, and a low resistance metal layer on the work function metal layer.Type: ApplicationFiled: January 4, 2019Publication date: May 9, 2019Inventors: Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Cheng-Ping Kuo, Kuan-Hao Tseng
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Publication number: 20190131183Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.Type: ApplicationFiled: November 7, 2017Publication date: May 2, 2019Inventors: Kuan-Hao Tseng, Chien-Ting Lin, Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Chueh-Fei Tai, Cheng-Ping Kuo
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Patent number: 10211313Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a first recess; forming ferroelectric (FE) layer in the first recess; forming a compressive layer on the FE layer; performing a thermal treatment process; removing the compressive layer; and forming a work function metal layer in the recess.Type: GrantFiled: August 16, 2017Date of Patent: February 19, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Cheng-Ping Kuo, Kuan-Hao Tseng
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Publication number: 20190019875Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a first recess; forming ferroelectric (FE) layer in the first recess; forming a compressive layer on the FE layer; performing a thermal treatment process; removing the compressive layer; and forming a work function metal layer in the recess.Type: ApplicationFiled: August 16, 2017Publication date: January 17, 2019Inventors: Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Cheng-Ping Kuo, Kuan-Hao Tseng
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Publication number: 20180308851Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.Type: ApplicationFiled: September 28, 2017Publication date: October 25, 2018Inventors: Jenn-Gwo HWU, Samuel C. PAN, Chien-Shun LIAO, Kuan-Hao TSENG