Patents by Inventor Kuan-Hsien LIU

Kuan-Hsien LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240161998
    Abstract: A deflecting plate includes a silicon-on-insulator (SOI) substrate. The SOI substrate includes: an insulator layer having a top surface and a bottom surface; a device layer coupled to the insulator layer at the top surface, wherein multiple deflecting apertures are disposed in the device layer, each of which extending from a top open end to a bottom open end through the device layer, and wherein the bottom open end is coplanar with the top surface of the insulator layer; and a handle substrate coupled to the insulator layer at the bottom surface, wherein a cavity is disposed in the handle substrate and extends from a cavity open end to a cavity bottom wall, and wherein the bottom wall is coplanar with the top surface of the insulator layer, such that the bottom open end of each deflecting aperture is exposed to the cavity.
    Type: Application
    Filed: September 10, 2023
    Publication date: May 16, 2024
    Inventors: Cheng-Hsien Chou, Yung-Lung Lin, Chun Liang Chen, Kuan-Liang Liu, Chin-Yu Ku, Jong-Yuh Chang
  • Patent number: 11978678
    Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: May 7, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
  • Patent number: 11962426
    Abstract: An Ethernet power supply receives a DC voltage through a bus positive terminal and a bus negative terminal, and is coupled to a load device. The Ethernet power supply includes a first control module and a second control module. The first control module is used to provide a first control signal through the bus negative terminal to confirm whether the load device is a valid load. The second control module is used to connect or disconnect a coupling relationship between the bus positive terminal and the first control module according to the load device being connected or not.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: April 16, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yung-Wei Peng, Kuan-Hsien Tu, Cheng-En Liu
  • Patent number: 11953964
    Abstract: An Ethernet power supply receives a DC voltage through a bus positive terminal and a bus negative terminal, and is coupled to a load device. The Ethernet power supply includes a first control module and a second control module. The first control module provides a first control signal through the bus negative terminal to confirm whether the load device is a valid load. The second control module is used to connect or disconnect a coupling relationship between the bus positive terminal and the first control module according to whether the load device is connected to the Ethernet power supply.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 9, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yung-Wei Peng, Kuan-Hsien Tu, Cheng-En Liu
  • Publication number: 20240096784
    Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 21, 2024
    Inventors: Meng-Hsien Lin, Hsing-Chih Lin, Ming-Tsong Wang, Min-Feng Kao, Kuan-Hua Lin, Jen-Cheng Liu, Dun-Nian Yaung, Ko Chun Liu
  • Patent number: 10475199
    Abstract: An optical measurement device and an optical measurement method for measuring a gap on an electronic device are provided. The optical measurement device includes an image capture device and an image processing device. The image capture device is used to capture an image including a gap. The electronic device includes a body and a component assembled on the body. The gap of the electronic device is existed between the body and the component. The image processing device is coupled to the image capture device. The image processing device is used to receive the image, and the image scanning operation is executed to the image to measure the breadth of the gap. The precise measurement result is quickly obtained.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: November 12, 2019
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Kuan-Hsien Liu, Ding-Chia Kao, Hao-Ting Hung, Yi-Ou Wang, You-Hung Tsai, Po Hung Huang
  • Publication number: 20170061648
    Abstract: An optical measurement device and an optical measurement method for measuring a gap on an electronic device are provided. The optical measurement device includes an image capture device and an image processing device. The image capture device is used to capture an image including a gap. The electronic device includes a body and a component assembled on the body. The gap of the electronic device is existed between the body and the component. The image processing device is coupled to the image capture device. The image processing device is used to receive the image, and the image scanning operation is executed to the image to measure the breadth of the gap. The precise measurement result is quickly obtained.
    Type: Application
    Filed: August 22, 2016
    Publication date: March 2, 2017
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Kuan-Hsien Liu, Ding-Chia Kao, Hao-Ting Hung, Yi-Ou Wang, You-Hung Tsai, Po Hung Huang
  • Publication number: 20140369559
    Abstract: An image recognition method includes the following steps: capturing a plurality of images; analyzing the images to get a target object; analyzing the target object to get color information and characteristic information; statistically computing a current image according to the color information and the characteristic information to get a probability distribution map; comparing a difference between the current image and a previous image of the current imago to get dynamic information; and recognizing the target object according to the probability distribution map and the dynamic information.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 18, 2014
    Inventors: Kuan-Hsien LIU, Ding-Chia KAO