Patents by Inventor Kuan-Hsuan Ku

Kuan-Hsuan Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369460
    Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.
    Type: Application
    Filed: June 9, 2022
    Publication date: November 16, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Kuang-Hsiu Chen, Wei-Chung Sun, Chao Nan Chen, Chun-Wei Yu, Kuan Hsuan Ku, Shao-Wei Wang
  • Patent number: 10483158
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Publication number: 20190122920
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Patent number: 10199260
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Patent number: 10128366
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: November 13, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
  • Publication number: 20180158943
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 7, 2018
    Inventors: Yu-Ying Lin, Kuan Hsuan KU, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu LIN, Chun Yao YANG, Yu-Ren Wang, Neng-Hui Yang
  • Patent number: 9929264
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: March 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
  • Publication number: 20170365703
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 21, 2017
    Inventors: Yu-Ying LIN, Kuan Hsuan KU, I-Cheng HU, Chueh-Yang LIU, Shui-Yen LU, Yu Shu LIN, Chun Yao YANG, Yu-Ren WANG, Neng-Hui YANG
  • Patent number: 9716165
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: July 25, 2017
    Assignee: United Microelectronics Corporation
    Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
  • Publication number: 20160163829
    Abstract: The present invention is a method of forming a recess structure. First of all, a substrate is provided, and a first ARC layer is entirely formed on the substrate, covering a first region and a second region thereof. Then, the first ARC layer in the second region is etched with a CH-based gas. Then, a first removing process is performed to form a first recess in the second region. Next, a second ARC layer is entirely formed on the substrate, covering the first region and the second region. Then, the second ARC layer in the first region is etched, also with the CH-based gas, and the CH-based gas includes at least one of CH4, C2H4, C3H6, CHF3, CH2F2, and CH3F. Finally, a second removing process is performed to form a second recess in the first region.
    Type: Application
    Filed: December 3, 2014
    Publication date: June 9, 2016
    Inventors: Kuan-Hsuan Ku, Jhen-Cyuan Li, Shui-Yen Lu