Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.

Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.

Abstract: A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.

Abstract: A method used in a flash memory controller includes: using a watchdog timer to automatically count a number and to generate a reset trigger signal to a processor if the number counted by the watchdog timer is higher than a threshold; after receiving the reset trigger signal from the watchdog timer, using the processor to copy registry information from at least one of processor, flash memory interface controller, and protocol controller, and then to control the memory controller to write the copied registry information into the dynamic random access memory device without rebooting a system of the flash memory controller.

Abstract: A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.

Abstract: A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.

Abstract: A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.

Abstract: The present invention provides a flash memory controller, where the flash memory controller includes a read-only memory, a processor and a cache, the read-only memory stores a program code, and the processor executes the program code to perform access a flash memory module. When the processor receives first data from a host, the processor stores the first data into a region of the cache, and the processor builds or updates a binary tree according to the first data, wherein the binary tree is used when the processor receives a read command from the host.

Abstract: A method used in a flash memory controller includes: using a watchdog timer to automatically count a number and to generate a reset trigger signal to a processor if the number counted by the watchdog timer is higher than a threshold; after receiving the reset trigger signal from the watchdog timer, using the processor to copy registry information from at least one of processor, flash memory interface controller, and protocol controller, and then to control the memory controller to write the copied registry information into the dynamic random access memory device without rebooting a system of the flash memory controller.

Abstract: A method used in a flash memory controller includes: using a watchdog timer to automatically count a number and to generate a reset trigger signal to a processor if the number counted by the watchdog timer is higher than a threshold; after receiving the reset trigger signal from the watchdog timer, using the processor to copy registry information from at least one of processor, flash memory interface controller, and protocol controller, and then to control the memory controller to write the copied registry information into the dynamic random access memory device without rebooting a system of the flash memory controller.

Abstract: The present invention provides a flash memory controller, where the flash memory controller includes a read-only memory, a processor and a cache, the read-only memory stores a program code, and the processor executes the program code to perform access a flash memory module. When the processor receives first data from a host, the processor stores the first data into a region of the cache, and the processor builds or updates a binary tree according to the first data, wherein the binary tree is used when the processor receives a read command from the host.

Abstract: A data storage device includes a flash memory and a flash memory controller. The flash memory controller operates the flash memory to store data, and stores a mapping table to record the mapping information between a plurality of logical addresses and a plurality of physical addresses of the flash memory. The mapping table is divided into a plurality of groups. Some of the groups are categorized into a first type of trim group and some of the logical addresses of each of the groups of the first type of trim group are included in a trim command. The flash memory controller performs the trim on the groups of the first type of trim group.

Abstract: A data storage device includes a flash memory and a flash memory controller. The flash memory controller operates the flash memory to store data, and stores a mapping table to record the mapping information between a plurality of logical addresses and a plurality of physical addresses of the flash memory. The mapping table is divided into a plurality of groups. Some of the groups are categorized into a first type of trim group and some of the logical addresses of each of the groups of the first type of trim group are included in a trim command. The flash memory controller performs the trim on the groups of the first type of trim group.

Abstract: A method for playing streaming data is suitable for an electronic device having a limited memory resource. The method includes: downloading a part of a streaming file to a buffer memory for playing, a size of the streaming file being larger than a capacity of the buffer memory; downloading another part of the streaming file to the buffer memory; and overwriting a played part of the streaming file stored in the buffer memory based on a usage status of the buffer memory.

Abstract: A method for playing streaming data is suitable for an electronic device having a limited memory resource. The method includes: downloading a part of a streaming file to a buffer memory for playing, a size of the streaming file being larger than a capacity of the buffer memory; downloading another part of the streaming file to the buffer memory; and overwriting a played part of the streaming file stored in the buffer memory based on a usage status of the buffer memory.