Abstract: A display device includes a display layer and a light guide plate (LGP) arranged on the display layer. A transparent plate is arranged between the LGP and the display layer, and the transparent plate houses a array of IR sensors. An IR source is arranged on the lateral surface of the LGP, and a scanning mirror is arranged on the lateral surface of the LGP. The IR sensors sense the IR light beams and determine whether a strength of the sensed IR light beams is decreased to below a predetermined threshold value, caused by a touch by a user, on the transparent plate at a location of said IR sensor, and send a signal associated with the touch to the control unit, the control unit is configured to receive the signal and determine the touch point according to the location of said IR sensor.

Abstract: A display device includes a display layer and a light guide plate (LGP) arranged on the display layer. The LGP includes a first surface facing away from the display layer, an opposite second surface, and a lateral surface between the first and second surfaces, the lateral surface having a light incident portion. A light source and a scanning mirror are arranged on the lateral surface of the LGP. The light source configured to emit a light beam toward the scanning mirror, the scanning mirror being reciprocally rotatable about a rotating axis at a given frequency, the scanning mirror configured to reflect and direct the light beam from the light source to enter into the LGP through the light incident portion.

Abstract: The light emitting diode package of the present invention uses photosensitive materials to form phosphor encapsulations or a phosphor layer, which can be fabricated by means of semiconductor processes in batch. Also, the concentration of phosphors in individual regions can be accurately and easily controlled by a laser printing process or by light-through holes. Accordingly, the optic effects of light emitting diode packages can be accurately adjusted.

Abstract: The light emitting diode package of the present invention uses photosensitive materials to form phosphor encapsulations or a phosphor layer, which can be fabricated by means of semiconductor processes in batch. Also, the concentration of phosphors in individual regions can be accurately and easily controlled by a laser printing process or by light-through holes. Accordingly, the optic effects of light emitting diode packages can be accurately adjusted.

Abstract: The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.

Abstract: A method of fabricating metal interconnects and an inter-metal dielectric layer thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the second metal interconnect pattern. The inter-metal dielectric layer is then planarized and the second metal interconnect pattern is exposed.

Abstract: The LED chip package of the present invention uses a semiconductor substrate as package substrate, which improves heat dissipation. Also, the LED chip package is incorporated with a planarization structure, which renders the LED chip and the substrate a substantially planar surface, thereby making formation of a planar patterned conductive layer possible. Accordingly, serial/parallel electrical connections between light emitting diode chips can be easily implemented by virtue of the planar patterned conductive layer.

Abstract: The light emitting diode package of the present invention uses photosensitive materials to form phosphor encapsulations or a phosphor layer, which can be fabricated by means of semiconductor processes in batch. Also, the concentration of phosphors in individual regions can be accurately and easily controlled by a laser printing process or by light-through holes. Accordingly, the optic effects of light emitting diode packages can be accurately adjusted.

Abstract: A chip package structure and method thereof uses a semiconductor substrate as a package substrate, which improve heat dissipation. Also, the chip package structure is incorporated with a planarization structure, which renders the chip and the package substrate a substantially planar surface, thereby making formation of a planar patterned conductive layer possible. Accordingly, electrical connections in series or in parallel between chips can be easily implemented by virtue of the planar patterned conductive layer.

Abstract: The LED chip package of the present invention uses a semiconductor substrate as package substrate, which improves heat dissipation. Also, the LED chip package is incorporated with a planarization structure, which renders the LED chip and the substrate a substantially planar surface, thereby making formation of a planar patterned conductive layer possible. Accordingly, serial/parallel electrical connections between light emitting diode chips can be easily implemented by virtue of the planar patterned conductive layer.

Abstract: The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.

Abstract: A method of fabricating micro mechanical moving member and metal interconnects thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the second metal interconnect pattern. The inter-metal dielectric layer is then planarized and the second metal interconnect pattern is exposed. After that, at least one micro mechanical moving member electrically connected to the second metal interconnect pattern is formed on the inter-metal dielectric layer by plating techniques.

Abstract: The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.

Abstract: A method of fabricating metal interconnects and an inter-metal dielectric layer thereof. A first metal interconnect pattern and a second metal interconnect pattern disposed thereon are formed on a substrate by plating processes. Subsequently, an inter-metal dielectric layer is formed on the substrate, the first metal interconnect pattern and the second metal interconnect pattern. The inter-metal dielectric layer is then planarized and the second metal interconnect pattern is exposed.

Abstract: A substrate is provided. The substrate includes a plurality of devices disposed in the substrate, a plurality of contact pads disposed on a surface of the substrate and electrically connected to the devices, and a surface dielectric layer positioned on the surface of the substrate. Thereafter, a surface treatment process including at least a plasma etching process is performed. Subsequently, at least a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a dielectric layer on a surface dielectric layer. The PECVD process is performed in a high frequency/low frequency alternating manner. Following that, a masking pattern on the dielectric layer is formed, and an anisotropic etching process is carried out to form a plurality of openings corresponding to the contact pads in the dielectric layer. The openings expose the contact pads, and each opening has an outwardly-inclined sidewall.

Abstract: The chip-type micro-connector includes a package substrate, a micro-connector disposed on the package structure, a plurality of chips, and a cap layer disposed on the micro-connector and the chips. The micro-connector includes a connection substrate, a plurality of connecting wires disposed in the connection substrate, and a plurality of contact pads exposed on a surface of the connection substrate and respectively connected to each connecting wire. The chips are coupled to one another via the contact pads and the connecting wires. The cap layer packages the micro-connector and the chips on the package substrate.

Abstract: The chip-type micro-connector includes a package substrate, a micro-connector disposed on the package structure, a plurality of chips, and a cap layer disposed on the micro-connector and the chips. The micro-connector includes a connection substrate, a plurality of connecting wires disposed in the connection substrate, and a plurality of contact pads exposed on a surface of the connection substrate and respectively connected to each connecting wire. The chips are coupled to one another via the contact pads and the connecting wires. The cap layer packages the micro-connector and the chips on the package substrate.

Abstract: A substrate is provided. The substrate includes a plurality of devices disposed in the substrate, a plurality of contact pads disposed on a surface of the substrate and electrically connected to the devices, and a surface dielectric layer positioned on the surface of the substrate. Thereafter, a surface treatment process including at least a plasma etching process is performed. Subsequently, at least a plasma enhanced chemical vapor deposition (PECVD) process is performed to form a dielectric layer on a surface dielectric layer. The PECVD process is performed in a high frequency/low frequency alternating manner. Following that, a masking pattern on the dielectric layer is formed, and an anisotropic etching process is carried out to form a plurality of openings corresponding to the contact pads in the dielectric layer. The openings expose the contact pads, and each opening has an outwardly-inclined sidewall.

Abstract: A substrate including a plurality of contact pads is provided. Thereafter, a photosensitive dielectric layer is formed on a surface of the substrate. Subsequently, an exposure-and-development process is preformed to partially remove the photosensitive dielectric layer so as to form a plurality of openings. The openings at least expose the contact pads, and the sidewall of each opening is inclined outwardly.