Patents by Inventor Kuan Lee

Kuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8148807
    Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: April 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Choon Kuan Lee, Chin Hui Chong, David J. Corisis
  • Patent number: 8138021
    Abstract: Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing apparatus for packaging semiconductor devices. One embodiment of an apparatus for packaging semiconductor devices comprises a first board having a front side, a backside, arrays of die contacts, arrays of first backside terminals electrically coupled to the die contacts, arrays of second backside terminals, and a plurality of individual package areas that have an array of the die contacts, an array of the first backside terminals, and an array of the second backside terminals.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: March 20, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, J. Michael Brooks, Choon Kuan Lee, Chin Hui Chong
  • Patent number: 8115112
    Abstract: Chip-scale packages and assemblies thereof are disclosed. The chip-scale package includes a core member of a metal or alloy having a recess for at least partially receiving a die therein and includes at least one flange member partially folded over another portion of the core member. Conductive traces extend from one side of the package over the at least one flange member to an opposing side of the package. Systems including the chip-scale packages and assemblies are also disclosed.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Chin Hui Chong, Choon Kuan Lee
  • Patent number: 8106491
    Abstract: A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of planar conductive members conductively coupling the first and second packaged integrated circuit devices to one another. A method is also disclosed which includes conductively coupling a plurality of extensions on a leadframe to each of a pair of stacked packaged integrated circuit devices and cutting the leadframe to singulate the extensions from one another.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: January 31, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Chin Hui Chong, Choon Kuan Lee
  • Publication number: 20120009044
    Abstract: An auxiliary member for coil nails includes a shank and a connection portion which is located at a lateral side of the shank, wherein the shank is pushed by a main pusher of a push mechanism. An extension portion is connected between the shank and the connection portion. The shank and the extension portion are non-parallel to each other, an axis of the shank is not parallel to an axis of the extension portion. The connection portion holds a shank of a last nail of the coil nails.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 12, 2012
    Applicant: SAMSON POWER TOOL CO., LTD.
    Inventor: Yi-Kuan Lee
  • Patent number: 8093702
    Abstract: Stacked microelectronic devices and methods of manufacturing stacked microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a plurality of electrically isolated, multi-tiered metal spacers on a front side of a first microelectronic die, and attaching a back-side surface of a second microelectronic die to individual metal spacers. In another embodiment, the method of manufacturing the microelectronic device may further include forming top-tier spacer elements on front-side wire bonds of the first die.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: January 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Edmund Koon Tian Lua, See Hiong Leow, Choon Kuan Lee
  • Patent number: 8070151
    Abstract: A sheet processing apparatus includes a sheet-table unit, a sheet-separating unit disposed at a downstream end of the sheet-table unit along a convey direction of the sheets, a convey unit arranged at a downstream end of sheet-separating unit, a discharge unit located at a downstream end of the convey unit, an sheet processing unit placed between the convey unit and the discharge unit, a speed sensor arranged at an upstream end of the sheet-separating unit for detecting a movement of each sheet for forming a sheet interval between two adjacent sheets, and an edge sensor located between the sheet-separating unit and the sheet processing unit. The edge sensor detects a front edge and a rear edge of each sheet passing therethrough, and sends corresponding control signals to a system controller which delays a predetermined time according to the control signals to control the sheet processing unit to start and stop processing.
    Type: Grant
    Filed: December 25, 2009
    Date of Patent: December 6, 2011
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventors: Chun-Kuan Lee, Yueh-Shing Lee, Shao-Yang Wu
  • Publication number: 20110266696
    Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.
    Type: Application
    Filed: July 12, 2011
    Publication date: November 3, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Choon Kuan Lee, David J. Corisis, Chong Chin Hui
  • Patent number: 8030751
    Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: October 4, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Choon Kuan Lee, David J. Corisis, Chin Hui Chong
  • Patent number: 7915077
    Abstract: Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked Package-On-Package modules are disclosed. The chip-scale package includes a core member of a metal or alloy having a recess for at least partially receiving a die therein and includes at least one flange member partially folded over another portion of the core member. Conductive traces extend from one side of the package over the at least one flange member to an opposing side of the package. Systems including the chip-scale packages and assemblies are also disclosed.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Chin Hui Chong, Choon Kuan Lee
  • Patent number: 7915726
    Abstract: Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed herein. A method of manufacturing a substrate in accordance with one embodiment of the invention includes forming a conductive trace on a first side of a sheet of non-conductive material, and forming a via through the non-conductive material from a second side of the sheet to the conductive trace. The method further includes removing a section of the non-conductive material to form an edge of the non-conductive material extending across at least a portion of the via. In one embodiment, forming the edge across the via exposes at least a portion of the second conductive trace for subsequent attachment to a terminal on a microelectronic die.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Chin Hui Chong, Choon Kuan Lee, David J. Corisis
  • Patent number: 7888185
    Abstract: Semiconductor device assemblies and systems that include at least one semiconductor device assembly include two or more semiconductor devices stacked one over another. Conductive pathways that extend around at least one side of at least one of the semiconductor devices provide electrical communication between conductive elements of the semiconductor devices, and optionally, a substrate. The conductive pathways may include self-supporting conductive leads or conductive traces carried by a substrate. Methods for forming semiconductor device assemblies having more than one semiconductor device include bending or wrapping at least one conductive pathway around a side of at least one semiconductor device and providing electrical communication between semiconductor devices of the assembly through the conductive pathways.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: February 15, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Chin Hui Chong, Choon Kuan Lee
  • Publication number: 20100320578
    Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.
    Type: Application
    Filed: September 2, 2010
    Publication date: December 23, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Choon Kuan Lee, Chong Chin Hui, David J. Corisis
  • Patent number: 7853763
    Abstract: A storage apparatus and an accessing method for the storage apparatus are provided. The storage apparatus comprises a plurality of data blocks, a plurality of spare blocks, and a calculation apparatus. The calculation apparatus is configured to (1) confirm whether a written block has to be updated, (2) select one of the spare blocks as the first moving block, (3) select one of the data blocks as second moving block, (4) store the first data of the second moving block into the first moving block, and (5) store the second data related to the written block into the second moving block. By updating a written block, data stored in other blocks are moved between each other. Blocks are charged and discharged so that data in the blocks are more accurate. The lifetime of the storage apparatus can be increased as well.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: December 14, 2010
    Assignee: Silicon Motion, Inc.
    Inventors: Wei-Yi Hsiao, Chun-Kun Lee, Chien-Kuan Lee
  • Publication number: 20100279466
    Abstract: Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing apparatus for packaging semiconductor devices. One embodiment of an apparatus for packaging semiconductor devices comprises a first board having a front side, a backside, arrays of die contacts, arrays of first backside terminals electrically coupled to the die contacts, arrays of second backside terminals, and a plurality of individual package areas that have an array of the die contacts, an array of the first backside terminals, and an array of the second backside terminals.
    Type: Application
    Filed: July 19, 2010
    Publication date: November 4, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: David J. Corisis, J. Michael Brooks, Choon Kuan Lee, Chin Hui Chong
  • Publication number: 20100276814
    Abstract: Methods for packaging microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One aspect of the invention is directed toward a method for packaging a microelectronic device that includes coupling an active side of a microelectronic die to a surface of a support member. The microelectronic die can have a backside opposite the active side, a peripheral side extending at least part way between the active side and the backside, and at least one through-wafer interconnect. The method can further include applying an encapsulant to cover a portion of the surface of the support member so that a portion of the encapsulant is laterally adjacent to the peripheral side, removing material from a backside of the microelectronic die to expose a portion of at least one through-wafer interconnect, and applying a redistribution structure to the backside of the microelectronic die.
    Type: Application
    Filed: June 29, 2010
    Publication date: November 4, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Choon Kuan Lee, Chin Hui Chong, David J. Corisis
  • Publication number: 20100276170
    Abstract: A pressure releasing device includes an end cap connected to a rear end of a body of the pneumatic tool and includes an engaging area. A cylinder is located in a chamber in the body of the pneumatic tool and partially located in the engaging area. The engaging area includes an axle hole and output holes are located around the axle hole. A groove is defined in an inside of the engaging area and includes a tapered surface. The cylinder includes intake holes communicating the chamber in the body. Release holes are defined in the cylinder and communicate with the groove of the engaging area. Two seals are respectively engaged with a first recess and a second recess. The release holes are located between the first and second recesses. Multiple output holes are defined in the cylinder and communicate between an outside of the cylinder and the second recess.
    Type: Application
    Filed: April 29, 2010
    Publication date: November 4, 2010
    Applicant: SAMSON POWER TOOL CO., LTD
    Inventor: YI-KUAN LEE
  • Patent number: 7816778
    Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: October 19, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Choon Kuan Lee, Chong Chin Hui, David J. Corisis
  • Publication number: 20100258997
    Abstract: A sheet processing apparatus includes a sheet-table unit, a sheet-separating unit disposed at a downstream end of the sheet-table unit along a convey direction of the sheets, a convey unit arranged at a downstream end of sheet-separating unit, a discharge unit located at a downstream end of the convey unit, an sheet processing unit placed between the convey unit and the discharge unit, a speed sensor arranged at an upstream end of the sheet-separating unit for detecting a movement of each sheet for forming a sheet interval between two adjacent sheets, and an edge sensor located between the sheet-separating unit and the sheet processing unit. The edge sensor detects a front edge and a rear edge of each sheet passing therethrough, and sends corresponding control signals to a system controller which delays a predetermined time according to the control signals to control the sheet processing unit to start and stop processing.
    Type: Application
    Filed: December 25, 2009
    Publication date: October 14, 2010
    Inventors: Chun-Kuan Lee, Yueh-Shing Lee, Shao-Yang Wu
  • Publication number: 20100244272
    Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.
    Type: Application
    Filed: June 9, 2010
    Publication date: September 30, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Choon Kuan Lee, Chin Hui Chong, David J. Corisis