Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a seed layer to cover a first passivation layer over a semiconductor substrate. The method also includes forming a metal layer to partially cover the seed layer by using the seed layer as an electrode layer in a first plating process and forming a metal pillar bump over the metal layer by using the seed layer as an electrode layer in a second plating process. In addition, the method includes forming a second passivation layer over the metal layer, wherein the second passivation layer includes a protrusion portion extending from a top surface of the second passivation layer and surrounding the sidewall of the metal pillar bump.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a seed layer to cover a first passivation layer over a semiconductor substrate. The method also includes forming a metal layer to partially cover the seed layer by using the seed layer as an electrode layer in a first plating process and forming a metal pillar bump over the metal layer by using the seed layer as an electrode layer in a second plating process. In addition, the method includes forming a second passivation layer over the metal layer, wherein the second passivation layer includes a protrusion portion extending from a top surface of the second passivation layer and surrounding the sidewall of the metal pillar bump.

Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.