Abstract: A LED lighting device comprises a seat including a baseplate and a sidewall surrounding the baseplate and forming a receiving space with the baseplate; an optical assembly disposed in the receiving space, wherein the optical assembly includes a light source component and an optical member; the optical member including a plurality of optical units, each of the optical units including a first optical member and a second optical member surrounding a periphery of the first optical member; the optical member covers the light source component; and an install border including a plurality of support elements, and the install border and an outer side of the sidewall forming a redundant space, wherein the optical member is clamped by the seat and the install border, and a power source is disposed in the redundant space.

Abstract: Coatings applicable to a variety of substrate articles, structures, materials, and equipment are described. In various applications, the substrate includes metal surface susceptible to formation of oxide, nitride, fluoride, or chloride of such metal thereon, wherein the metal surface is configured to be contacted in use with gas, solid, or liquid that is reactive therewith to form a reaction product that is deleterious to the substrate article, structure, material, or equipment. The metal surface is coated with a protective coating preventing reaction of the coated surface with the reactive gas, and/or otherwise improving the electrical, chemical, thermal, or structural properties of the substrate article or equipment. Various methods of coating the metal surface are described, and for selecting the coating material that is utilized.

Abstract: An electronic memory device includes a memory-cell circuit. The electronic memory device also includes a non-memory-cell circuit. The non-memory cell circuit includes an active region. The active region extends in a first direction in a top view. The active region includes a first segment and a second segment. The first segment has a first dimension measured in a second direction in the top view. The second segment has a second dimension measured in the second direction different from the first direction in the top view. The second dimension is different from the first dimension.

Abstract: A method of decoding a picture frame from a bitstream includes grouping N tiles of the picture frame into P sub-pictures, the P sub-pictures being non-overlapping with each other, a first sub-picture of the P sub-pictures comprising Q columns of tiles, N being an integer exceeding 1, P, Q being positive integers, and partitioning a first column of tiles of the Q columns of tiles into M sub-slices, the M sub-slices being non-overlapping with each other, M being an integer exceeding 1. The method further includes obtaining first tile information from a memory prior to decoding a current sub-slice of the M sub-slices, a first processor decoding the current sub-slice of the M sub-slices according to the first tile information, and storing second tile information in the memory upon completion of decoding the current sub-slice of the M sub-slices.

Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, a method includes: selecting a first interface to receive higher-speed-type data at a first clock frequency; transferring the higher-speed-type data with a first speed along a first data path from the first interface through a first logic circuit to a driving circuit; outputting the higher-speed-type data by the driving circuit; selecting a second interface to receive lower-speed-type data at a second clock frequency that is same as the first clock frequency; transferring the lower-speed-type data with a second speed along a second data path from the second interface through a second logic circuit to the driving circuit, the first speed being higher than the second speed; and outputting the lower-speed-type data by the driving circuit.

Abstract: A method for re-triggering wakeup to handle time skew between a scalar operation and a vector operation is provided. The method includes: initiating, before a Load-Store (LST) pipeline completes an execution of a load operation corresponding to a vector micro-operation (uop) dispatched to a baler issue queue, a respective load operation in a Load (LD) pipeline corresponding to the vector uop; triggering a speculative wakeup from the LD pipeline during an execution of the respective load operation; triggering a second wakeup corresponding to the speculative wakeup from the LD pipeline; and waking up, based on the second wakeup, the vector micro-operation in the baler issue queue of the baler unit.

Abstract: An image compensation circuit for an image sensor includes a gain amplifier, a compensation control circuit, a memory and a digital-to-analog converter (DAC). The gain amplifier is used for receiving a plurality of image signals from the image sensor and amplifying the plurality of image signals. The compensation control circuit is used for generating a plurality of compensation values for the plurality of image signals. The memory, coupled to the compensation control circuit, is used for storing the plurality of compensation values. The DAC, coupled to the memory and the gain amplifier, is used for converting the plurality of compensation values into a plurality of compensation voltages, respectively, to compensate the plurality of image signals with the plurality of compensation voltages.

Abstract: A method and a system for dynamically tuning thermal design power and a non-transitory computer-readable storage medium are described. The system is configured to dynamically tune turbo boost mode operation parameters of a central processing unit (CPU), independent of related settings of a turbo boost operation state of the CPU. In an embodiment, a controller is configured to send a power tuning signal to a basic input/output system (BIOS) to directly intervene and tune a real-time operating power of the CPU.

Abstract: A terminal structure includes a terminal body, a locking means formed on at least one face of the terminal body, an insertion unit extending from a first end of the terminal body, and a holding mechanism extending from a second end of the terminal body. The insertion unit is mounted on a circuit board. The circuit board defines multiple conducting holes. The insertion unit is inserted into and locked in one of the conducting holes of the circuit board. The holding mechanism includes two opposite clamping arms and a clamping space defined between the two clamping arms. An electronic element is held by the holding mechanism. The electronic element has multiple lead legs. One of the lead legs of the electronic element is clamped between the two clamping arms and held in the clamping space.

Abstract: A method of forming a semiconductor device is provided. The method includes mounting a semiconductor die on a die pad of a leadframe. The die pad includes a central opening configured to expose a central portion of the semiconductor die. A first end of a bond wire is attached to a bond pad of the semiconductor die and a second end of the bond wire is attached to a lead of the leadframe. An encapsulant encapsulates the semiconductor die and the leadframe. A portion of the lead and a portion of the die pad are exposed and protruded through the encapsulant.

Abstract: A LED lighting device, comprising: a base which has a bottom plate and a side wall, a cavity being formed between the bottom plate and the side wall; an optical component which covers one side of the base in a light-emitting direction of the LED lighting device; and a light source which is provided in the cavity of the base and comprises a circuit board and several LED arrays, the LED arrays comprising LED lamp beads fixed on the circuit board. The optical component comprises an optical unit, and the optical unit comprises a plurality of first optical components and a plurality of second optical components which correspond to the first optical components.

Abstract: An electric nail gun includes a main body, a limiting mechanism, an active mechanism, a passive mechanism, a magnetic attraction mechanism, a striking nail mechanism, a safety mechanism and a lithium battery case. The present invention allows users to activate a motor switch of the active mechanism while holding the main body, enabling beforehand operation of the motor to drive a wheel to reach the preset speed. Once a trigger switch is activated, magnetic force is generated by an electromagnet for attracting a cam to pivot and be pushed by a driving block of the wheel, causing temporary synchronous rotation state of a pulley and the wheel and displacement of the striking nail mechanism indirectly induced by engagement between the pulley and belt for nailing action.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Abstract: Disclosed is an electronic assembly that includes a heat sink with a groove that is cut on a surface of the heat sink. A thermal interface material is disposed between the heat sink and an electronic device. A compressible filler disposed in the groove surrounds and confines the thermal interface material.

Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.

Abstract: In some example embodiments, there may be provided a method that includes receiving, at a machine learning model, an input for a task of the machine learning model, wherein the machine learning model comprises a plurality of residual blocks augmented with a plurality of augmented weight blocks that sample intermediate features from the plurality of residual blocks; applying the input to the machine learning model to perform the task, wherein the applying comprises applying the plurality of intermediate features, which are obtained from the plurality of residual blocks, to the plurality of augmented weight blocks to form a plurality of intermediate outputs; and generating an output of the machine learning model, wherein the output is generated using at least on a combination of the plurality of intermediate outputs. Related systems, methods, and articles of manufacture are also disclosed.

Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

Abstract: An oscillator device includes a current generating circuit, a current source and an oscillator circuit. The current generating circuit generates first, second, third and fourth currents. The current source generates a first reference current according to the first current and the second current and a second reference current according to the third current and the fourth current. The oscillator circuit receives the first reference current and the second reference current and generates an oscillating signal. The temperature coefficient of the oscillator circuit is compensated for by the first reference current and the second reference current. At least two of the first current, the second current, the third current and the fourth current are different. The first reference current is different from the second reference current.