Patents by Inventor Kuan-Lin Yeh

Kuan-Lin Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240313072
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 19, 2024
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • Patent number: 11990525
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • Publication number: 20230361124
    Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.
    Type: Application
    Filed: July 19, 2023
    Publication date: November 9, 2023
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang
  • Publication number: 20230317502
    Abstract: A method for manufacturing an electronic package and a suction device are provided. The method includes: providing an electronic component having a first surface and including at least one conductive stud on the first surface; providing a suction device having at least one recess; and moving the electronic component with the suction device, wherein an edge of the at least one recess does not overlap the at least one conductive stud from a top view while moving the electronic component with the suction device.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun Hung TSAI, Chenghan SHE, Kuo-Chih HUANG, Kuan-Lin YEH
  • Patent number: 11749683
    Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang
  • Publication number: 20230102368
    Abstract: A first dielectric layer is formed over upper and side surfaces of a semiconductor fin structure. A mask layer is formed over a first portion of the first dielectric layer disposed over the upper surface of the fin structure. The mask layer and the first dielectric layer have different material compositions. Second portions of the first dielectric layer disposed on side surfaces of the fin structure are etched. The mask layer protects the first portion of the first dielectric layer from being etched. A second dielectric layer is formed over the mask layer and the side surfaces of the fin structure. An oxidation process is performed to convert the mask layer into a dielectric material having substantially a same material composition as the first or second dielectric layer. The dielectric material and remaining portions of the first or second dielectric layer collectively serve as a gate dielectric of a transistor.
    Type: Application
    Filed: December 5, 2022
    Publication date: March 30, 2023
    Inventors: Pang-Hsuan Liu, Kuan-Lin Yeh, Chun-Sheng Liang, Hsin-Che Chiang
  • Patent number: 11521971
    Abstract: A first dielectric layer is formed over upper and side surfaces of a semiconductor fin structure. A mask layer is formed over a first portion of the first dielectric layer disposed over the upper surface of the fin structure. The mask layer and the first dielectric layer have different material compositions. Second portions of the first dielectric layer disposed on side surfaces of the fin structure are etched. The mask layer protects the first portion of the first dielectric layer from being etched. A second dielectric layer is formed over the mask layer and the side surfaces of the fin structure. An oxidation process is performed to convert the mask layer into a dielectric material having substantially a same material composition as the first or second dielectric layer. The dielectric material and remaining portions of the first or second dielectric layer collectively serve as a gate dielectric of a transistor.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pang-Hsuan Liu, Kuan-Lin Yeh, Chun-Sheng Liang, Hsin-Che Chiang
  • Publication number: 20220293752
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 15, 2022
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • Publication number: 20220246613
    Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 4, 2022
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang
  • Patent number: 11349002
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • Publication number: 20220157812
    Abstract: A first dielectric layer is formed over upper and side surfaces of a semiconductor fin structure. A mask layer is formed over a first portion of the first dielectric layer disposed over the upper surface of the fin structure. The mask layer and the first dielectric layer have different material compositions. Second portions of the first dielectric layer disposed on side surfaces of the fin structure are etched. The mask layer protects the first portion of the first dielectric layer from being etched. A second dielectric layer is formed over the mask layer and the side surfaces of the fin structure. An oxidation process is performed to convert the mask layer into a dielectric material having substantially a same material composition as the first or second dielectric layer. The dielectric material and remaining portions of the first or second dielectric layer collectively serve as a gate dielectric of a transistor.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Inventors: Pang-Hsuan Liu, Kuan-Lin Yeh, Chun-Sheng Liang, Hsin-Che Chiang
  • Patent number: 11315924
    Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang
  • Publication number: 20220102509
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • Publication number: 20210408000
    Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang
  • Patent number: 10163718
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hsueh Li, Chih-Yang Yeh, Chun-Chan Hsiao, Kuan-Lin Yeh, Yuan-Sheng Huang
  • Publication number: 20180012806
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.
    Type: Application
    Filed: September 8, 2017
    Publication date: January 11, 2018
    Inventors: Po-Hsueh LI, Chih-Yang YEH, Chun-Chan HSIAO, Kuan-Lin YEH, Yuan-Sheng HUANG
  • Patent number: 9779997
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hsueh Li, Chih-Yang Yeh, Chun-Chan Hsiao, Kuan-Lin Yeh, Yuan-Sheng Huang
  • Publication number: 20170194209
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.
    Type: Application
    Filed: March 11, 2016
    Publication date: July 6, 2017
    Inventors: Po-Hsueh LI, Chih-Yang YEH, Chun-Chan HSIAO, Kuan-Lin YEH, Yuan-Sheng HUANG
  • Patent number: 7429726
    Abstract: A system for displaying and capturing images is provided. The system includes a display unit, a detection module. The display unit provides a first light according to a scan signal and a data signal. The detection module captures a second light and comprises a photo detection unit, a transformation unit, and a switch unit. The photo detection unit detects intensity of the second light. The transformation unit transforms the light intensity into a voltage signal. The switch unit outputs the voltage signal according to a selection signal.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: September 30, 2008
    Assignee: TPO Displays Corp.
    Inventor: Kuan-Lin Yeh
  • Publication number: 20080067329
    Abstract: A system for displaying and capturing images. The system comprises a display unit, a detection module. The display unit provides a first light according to a scan signal and a data signal. The detection module captures a second light and comprises a photo detection unit, a transformation unit, and a switch unit. The photo detection unit detects intensity of the second light. The transformation unit transforms the light intensity into a voltage signal. The switch unit outputs the voltage signal according to a selection signal.
    Type: Application
    Filed: September 19, 2006
    Publication date: March 20, 2008
    Applicant: TPO DISPLAYS CORP.
    Inventor: Kuan-Lin Yeh