Patents by Inventor Kuan-Lun Chang
Kuan-Lun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113214Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first channel member suspended over a substrate and a second channel member suspended over the first channel member and spaced apart from the first channel member along a first direction. The semiconductor structure also includes a gate structure wrapping around the first channel member and the second channel member and a dielectric structure encircled by the first channel member, the second channel member, the gate structure, and the source/drain structure. In addition, the dielectric structure includes a porous material or an air gap. The semiconductor structure also includes a first epitaxial layer attached to the first channel member, and the first epitaxial layer has a first extending portion protruding from a bottom surface of the first channel member along the first direction and extending into the dielectric structure.Type: ApplicationFiled: March 3, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Lun Chang, Kuan-Ting Pan, Wei-Yang Lee
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Patent number: 11948879Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.Type: GrantFiled: July 27, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240105806Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, a source/drain feature coupled to the vertical stack of channel members and adjacent the gate structure; and a dielectric feature disposed between the source/drain feature and the substrate, in a cross-sectional view, the dielectric feature includes a V-shape sidewall surface.Type: ApplicationFiled: March 9, 2023Publication date: March 28, 2024Inventors: Che-Lun Chang, Kuan-Ting Pan, Wei-Yang Lee
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Publication number: 20240096996Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Lo-Heng Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 11916072Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.Type: GrantFiled: July 22, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Chuan You, Chia-Hao Chang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20130288421Abstract: A method of fabricating a differential doped solar cell is provided. The method comprises the steps of (a) providing a light doped semiconductor substrate; (b) forming a heavy doped layer having the same type of dopant used in step (a) on a front surface of the semiconductor substrate; and (c) forming an emitter layer having a different type of dopant used in step (a) on a surface of the heavy doped layer to constitute a p-n junction with the heavy doped layer.Type: ApplicationFiled: April 16, 2013Publication date: October 31, 2013Applicant: BIG SUN Energy Technology IncorporationInventors: Chi-Hsiung CHANG, Kuan-Lun CHANG, Hung-Yi CHANG, Yi-Min PAN, Jun-Min WU, Ying-Yen CHIU
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Patent number: 8445311Abstract: A method of fabricating a differential doped solar cell is provided. The method comprises the steps of (a) providing a light doped semiconductor substrate; (b) forming a heavy doped layer having the same type of dopant used in step (a) on a front surface of the semiconductor substrate; and (c) forming an emitter layer having a different type of dopant used in step (a) on a surface of the heavy doped layer to constitute a p-n junction with the heavy doped layer.Type: GrantFiled: November 22, 2011Date of Patent: May 21, 2013Assignee: Big Sun Energy Technology IncorporationInventors: Chi-Hsiung Chang, Kuan-Lun Chang, Hung-Yi Chang, Yi-Min Pan, Jun-Min Wu, Ying-Yen Chiu
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Publication number: 20120164779Abstract: A method of fabricating a differential doped solar cell is provided. The method comprises the steps of (a) providing a light doped semiconductor substrate; (b) forming a heavy doped layer having the same type of dopant used in step (a) on a front surface of the semiconductor substrate; and (c) forming an emitter layer having a different type of dopant used in step (a) on a surface of the heavy doped layer to constitute a p-n junction with the heavy doped layer.Type: ApplicationFiled: November 22, 2011Publication date: June 28, 2012Inventors: Chi-Hsiung CHANG, Kuan-Lun Chang, Hung-Yi Chang, Yi-Min Pan, Jun-Min Wu, Ying-Yen Chiu
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Patent number: 7372102Abstract: A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided.Type: GrantFiled: November 10, 2005Date of Patent: May 13, 2008Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Patent number: 7317221Abstract: A stacked integrated circuit (IC) MIM capacitor structure and method for forming the same the MIM capacitor structure including a first MIM capacitor structure formed in a first IMD layer comprising an first upper and first lower electrode portions; at least a second MIM capacitor structure arranged in stacked relationship in an overlying IMD layer comprising a second upper electrode and second lower electrode to form an MIM capacitor stack; wherein, the first lower electrode is arranged in common electrical signal communication comprising metal filled vias with the second upper electrode and the first upper electrode is arranged in common electrical signal communication with the second lower electrode.Type: GrantFiled: December 4, 2003Date of Patent: January 8, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuan-Lun Chang, Chuan-Ying Lee, Chun-Hon Chen
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Patent number: 7250344Abstract: A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.Type: GrantFiled: November 10, 2005Date of Patent: July 31, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Patent number: 7238969Abstract: A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.Type: GrantFiled: June 14, 2005Date of Patent: July 3, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Hsun Wu, Kuan-Lun Chang, Chuan-Ying Lee, Jian-Hsing Lee
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Publication number: 20060278928Abstract: A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.Type: ApplicationFiled: June 14, 2005Publication date: December 14, 2006Inventors: Yi-Hsun Wu, Kuan-Lun Chang, Chuan-Ying Lee, Jian-Hsing Lee
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Publication number: 20060063349Abstract: A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.Type: ApplicationFiled: November 10, 2005Publication date: March 23, 2006Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Publication number: 20060063389Abstract: A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided.Type: ApplicationFiled: November 10, 2005Publication date: March 23, 2006Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Patent number: 7015086Abstract: A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug.Type: GrantFiled: February 5, 2004Date of Patent: March 21, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Publication number: 20050176214Abstract: A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug.Type: ApplicationFiled: February 5, 2004Publication date: August 11, 2005Inventors: Kuan-Lun Chang, Ruey-Hsin Liu, Tsyr-Shyang Liou, Chih-Min Chiang, Jun-Lin Tsai
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Publication number: 20050121744Abstract: A stacked integrated circuit (IC) MIM capacitor structure and method for forming the same the MIM capacitor structure including a first MIM capacitor structure formed in a first IMD layer comprising an first upper and first lower electrode portions; at least a second MIM capacitor structure arranged in stacked relationship in an overlying IMD layer comprising a second upper electrode and second lower electrode to form an MIM capacitor stack; wherein, the first lower electrode is arranged in common electrical signal communication comprising metal filled vias with the second upper electrode and the first upper electrode is arranged in common electrical signal communication with the second lower electrode.Type: ApplicationFiled: December 4, 2003Publication date: June 9, 2005Inventors: Kuan-Lun Chang, Chuan-Ying Lee, Chun-Hon Chen
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Patent number: 6847061Abstract: During the conventional manufacture of HBTs, implant damage occurs which leads to enhanced internal base diffusion. This problem has been overcome by making the base and base contact area from a single, uniformly doped layer of silicon-germanium. Instead of an ion implant step to selectively reduce the resistance of this layer away from the base, a layer of polysilicon is selectively deposited (using selective epi deposition) onto only that part. Additionally, the performance of the polysilicon emitter is enhanced by means a brief thermal anneal that drives a small amount of opposite doping type silicon into the SiGe base layer.Type: GrantFiled: April 3, 2003Date of Patent: January 25, 2005Assignee: Taiwan Semiconductor Manufacturing Co.Inventors: Chun-Lin Tsai, Denny D. Tang, Chih-Min Chiang, Kuan-Lun Chang, Tsyr Shyang, Ruey-Hsin Liu
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Publication number: 20040195587Abstract: During the conventional manufacture of HBTs, implant damage occurs which leads to enhanced internal base diffusion. This problem has been overcome by making the base and base contact area from a single, uniformly doped layer of silicon-germanium. Instead of an ion implant step to selectively reduce the resistance of this layer away from the base, a layer of polysilicon is selectively deposited (using selective epi deposition) onto only that part. Additionally, the performance of the polysilicon emitter is enhanced by means a brief thermal anneal that drives a small amount of opposite doping type silicon into the SiGe base layer.Type: ApplicationFiled: April 3, 2003Publication date: October 7, 2004Inventors: Chun-Lin Tsai, Denny D. Tang, Chih-Min Chiang, Kuan-Lun Chang, Tsyr Shyang, Ruey-Hsin Liu