Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The gate structure includes a gate dielectric layer, a first conductive layer over the first conductive layer. The gate structure includes a fill layer over the first conductive layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a top surface of the gate dielectric layer is lower than a top surface of the protection layer and higher than a top surface of the first conductive layer.

Abstract: A method includes providing a first channel layer and a second channel layer over a substrate; forming a first patterned hard mask covering the first channel layer and exposing the second channel layer; selectively depositing a cladding layer on the second channel layer and not on the first patterned hard mask; performing a first thermal drive-in process; removing the first patterned hard mask; after removing the first patterned hard mask, forming an interfacial dielectric layer on the cladding layer and the first channel layer; and forming a high-k dielectric layer on the interfacial dielectric layer.

Abstract: Present disclosure provides a method for forming a semiconductor structure, including forming a dielectric layer over a semiconductor substrate, patterning an insulator stripe over the semiconductor substrate, including forming an insulator layer over the semiconductor substrate and at a bottom of the insulator stripe, depositing a semiconductor capping layer continuously over the insulator stripe, wherein the semiconductor capping layer includes crystalline materials, wherein the semiconductor capping layer is free from being in direct contact with the semiconductor substrate, and cutting off the semiconductor capping layer between the insulator stripes, forming a gate, wherein the gate is in direct contact with the semiconductor capping layer, a first portion of the semiconductor capping layer covered by the gate is configured as a channel structure, and forming a conductible region at a portion of the insulator stripe not covered by the gate stripe by a regrowth operation.

Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

Abstract: A semiconductor device includes a gate structure, a source/drain epitaxial structure, a front-side interconnection structure, a backside via, an isolation material, and a sidewall spacer. The source/drain epitaxial structure is on a side of the gate structure. The front-side interconnection structure is on a front-side of the source/drain epitaxial structure. The backside via is connected to a backside of the source/drain epitaxial structure. The isolation material is on a side of the backside via and in contact with the gate structure. The sidewall spacer is sandwiched between the backside via and the isolation material. A height of the isolation material is greater than a height of the sidewall spacer.

Abstract: A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 ? to about 20 ?.

Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

Abstract: A device includes a substrate, first and second gate structures, first and second hybrid fins, and first and second sidewalls. The first gate structure is over and surrounds a first vertical stack of nanostructures. The second gate structure is over and surrounds a second vertical stack of nanostructures. The second gate structure and the first gate structure extend along a first direction, and are laterally separated from each other in a second direction, the second direction being substantially perpendicular to the first direction. The first hybrid fin extends through and under the first gate structure and the second gate structure, the extending being along the second direction. The second hybrid fin is between the first gate structure and the second gate structure. The second hybrid fin has: a first sidewall that abuts the first gate structure; and a second sidewall that abuts the second gate structure.

Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.

Abstract: A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The method for forming a semiconductor device includes forming a first stack of channel structures that extends between a source terminal and a drain terminal of a first transistor in a first region of the semiconductor device. The first stack of channel structures includes a first channel structure and a second channel structure. The method further includes forming a first gate structure that wraps around the first stack of channel structures with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes forming a stack of a first type and a second type epitaxial layers on a frontside of a semiconductor substrate, patterning the stack to form a fin-shaped structure, depositing a dielectric layer on sidewalls of the fin-shaped structure, and recessing the dielectric layer to expose a top portion of the fin-shaped structure. A top surface of the recessed dielectric layer is above a bottom surface of the stack. The exemplary manufacturing method also includes forming a gate structure over the top portion of the fin-shaped structure, etching the semiconductor substrate from a backside of the semiconductor substrate, and etching at least a bottommost first type epitaxial layer and a bottommost second type epitaxial layer through the trench.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.

Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall, and a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.

Abstract: A semiconductor device includes a substrate, a first dielectric fin, a semiconductor fin, a metal gate structure, an epitaxy structure, and a contact etch stop layer. The first dielectric fin is disposed over the substrate. The semiconductor fin is disposed over the substrate, in which along a lengthwise direction of the first dielectric fin and the semiconductor fin, the first dielectric fin is in contact with a first sidewall of the semiconductor fin. The metal gate structure crosses the first dielectric fin and the semiconductor fin. The epitaxy structure is over and in contact with the semiconductor fin. The contact etch stop layer is over and in contact with first dielectric fin.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A semiconductor structure includes a semiconductor fin, a doped dielectric fin, a shallow trench isolation (STI) oxide, a gate structure, and source/drain regions. The semiconductor fin upwardly extends from a substrate. The doped dielectric fin upwardly extends above the substrate. The doped dielectric fin is implanted with an impurity therein. The STI oxide laterally surrounds a lower portion of the semiconductor fin and a lower portion of the doped dielectric fin. The gate structure extends across the semiconductor fin and the doped dielectric fin. The source/drain regions are on the semiconductor fin and at opposite sides of the gate structure.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece that has a substrate, a first plurality of channel members, a second plurality of channel members, a first gate structure engaging the first plurality of channel members, a second gate structure engaging the second plurality of channel members, a hybrid fin disposed between the first and second gate structures, and an isolation feature disposed under the hybrid fin. The method also includes forming a metal cap layer at a frontside of the workpiece. The metal cap layer electrically connects the first and second gate structures. The method also includes etching the isolation feature, etching the hybrid fin, etching the metal cap layer, and depositing a dielectric material to form a gate isolation feature disposed between the first and second gate structures.

Abstract: A semiconductor device includes a substrate, an isolation feature over the substrate, a first device fin protruding from the substrate and through the isolation feature, and a second device fin protruding from the substrate and through the isolation feature. The semiconductor device also includes a dielectric fin disposed between the first and second device fins and a metal gate stack engaging the first and second device fins. The dielectric fin separates the metal gate stack into first and second segments and provides electrical isolation between the first and second segments. A portion of the isolation feature is directly under a bottom surface of the dielectric fin.