Patents by Inventor Kuan Pei Yap

Kuan Pei Yap has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094809
    Abstract: An eye tracking system with in-optical-assembly plane illumination is described. Side-emitting light emitting diodes (LEDs) aligned with a plane of an optical assembly of a near-eye display device are used to illuminate the eye of a user and generate glints that can be detected by an eye tracking camera. When a corrective optical lens or similar element is included in the optical assembly that may distort illumination beams from the light emitting diodes (LEDs), the distortion is mitigated by using in-package or externally modified LEDs that provide angled beams. In addition to in-package level mitigations such as reflectors or labels, edge portions of the distorting optical elements may be shaped or complemented with refractive elements to redirect the beams toward the eye.
    Type: Application
    Filed: June 27, 2023
    Publication date: March 21, 2024
    Applicant: Meta Platforms Technologies, LLC
    Inventors: Qi ZHANG, Chad Lichtenhan, Morteza Karami, Kuan Pei Yap, Mehmet Mutlu
  • Publication number: 20240012246
    Abstract: Systems, methods, and devices for eye tracking are provided. A device may include at least one printed circuit board including a shape around a lens of the device. The device may also include a plurality of light emitting diodes arranged around the shape of the lens. The plurality of light emitting diodes may be configured to connect to the at least one printed circuit board. The plurality of light emitting diodes may also be configured to illuminate light directed to at least one eye of a user to cause at least one reflection of the at least one eye.
    Type: Application
    Filed: April 25, 2023
    Publication date: January 11, 2024
    Inventors: Wei Wu, Anthony Diego Draper, Daniel Turowski, Mehmet Mutlu, Alfredo Bismuto, Qi Zhang, Kuan Pei Yap
  • Publication number: 20240012244
    Abstract: An eye-tracking system may include an optical assembly with integrated micro light emitting diodes. The optical assembly may include a substrate and a flexible printed circuit board assembly bonded to the substrate. Micro light emitting diodes may also be bonded to the substrate. A plurality of conductors may be laminated in the substrate. The conductors may electrically connect the micro light emitting diodes to the printed circuit board assembly. An optically clear adhesive layer may be adhered to the substrate. The optically clear adhesive layer may include an anti-reflective layer and an optical adhesive layer to arranged in a stacked configuration.
    Type: Application
    Filed: July 11, 2022
    Publication date: January 11, 2024
    Applicant: Meta Platforms Technologies, LLC
    Inventors: Mehmet MUTLU, Wei Wu, Alfredo Bismuto, Qi Zhang, Kuan Pei Yap
  • Publication number: 20240012473
    Abstract: Systems, methods, and devices for eye tracking are provided. A device may include a multi-functional optical module including a plurality of optical lens layers. The device may include a layer, among the plurality of optical lens layers, including a patterned substrate including a plurality of light emitting diodes in a field of view of the layer and a plurality of wires configured to connect to a printed circuit board assembly. The light emitting diodes in the field of view may be configured to illuminate light directed to at least one eye of a user to cause at least one reflection of the at least one eye.
    Type: Application
    Filed: April 25, 2023
    Publication date: January 11, 2024
    Inventors: Wei Wu, Mehmet Mutlu, Alfredo Bismuto, Qi Zhang, Kuan Pei Yap
  • Patent number: 6468906
    Abstract: An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: October 22, 2002
    Assignees: Chartered Semiconductor Manufacturing Ltd., National University of Singapore, Namyang Technological University of Singapore, Institute of Microelectronics
    Inventors: Lap Chan, Kuan Pei Yap, Kheng Chok Tee, Flora S. Ip, Wye Boon Loh
  • Patent number: 6100195
    Abstract: An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: August 8, 2000
    Assignees: Chartered Semiconductor Manu. Ltd., National University of Singapore, Nahyang Techn. Univ. of Singapore, Institute of Microelectronics
    Inventors: Lap Chan, Kuan Pei Yap, Kheng Chok Tee, Flora S. Ip, Wye Boon Loh