Patents by Inventor Kuan-Po Chen
Kuan-Po Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9095019Abstract: By diverting a small amount of current from a string of LED(s) powered by a LED driver at low current levels in a process of dimming the LED string, performance of the LED string light emission is improved.Type: GrantFiled: February 5, 2014Date of Patent: July 28, 2015Assignee: DiCon Fiberoptics, Inc.Inventors: Kuan-Po Chen, Ho-Shang Lee
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Publication number: 20140361694Abstract: By diverting a small amount of current from a string of LED(s) powered by a LED driver at low current levels in a process of dimming the LED string, performance of the LED string light emission is improved.Type: ApplicationFiled: February 5, 2014Publication date: December 11, 2014Applicant: DiCon Fiberoptics Inc.Inventors: Kuan-Po Chen, Ho-Shang Lee
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Patent number: 8729635Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a stacked gate structure, doped regions and high stress material layers. The stacked gate structure is located on the substrate. The stacked gate structure includes at least a dielectric layer and a gate sequentially disposed over the substrate. The doped regions are disposed in the substrate on each side of the stacked gate structure. The high stress material layers are disposed on the substrate to cover the doped regions. The high stress material layers can increase the mobility of the carriers in the doped regions and hence accelerate the operating speed of the device.Type: GrantFiled: January 18, 2006Date of Patent: May 20, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Kuan-Po Chen, Mu-Yi Liu
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Patent number: 7875938Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.Type: GrantFiled: December 1, 2008Date of Patent: January 25, 2011Assignee: Macronix International Co., Ltd.Inventors: Mu-Yi Liu, Chia-Lun Hsu, Ichen Yang, Kuan-Po Chen, Tao-Cheng Lu
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Publication number: 20090108345Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.Type: ApplicationFiled: December 1, 2008Publication date: April 30, 2009Applicant: Macronix International Co., Ltd.Inventors: Mu-Yi Liu, Chia-Lun Hsu, Ichen Yang, Kuan-Po Chen, Tao-Cheng Lu
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Patent number: 7473625Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased whilst maintaining a high breakdown voltage.Type: GrantFiled: April 7, 2005Date of Patent: January 6, 2009Assignee: Macronix International Co., Ltd.Inventors: Mu-Yi Liu, Chia-Lun Hsu, Ichen Yang, Kuan-Po Chen, Tao-Cheng Lu
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Publication number: 20070164370Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a stacked gate structure, doped regions and high stress material layers. The stacked gate structure is located on the substrate. The stacked gate structure includes at least a dielectric layer and a gate sequentially disposed over the substrate. The doped regions are disposed in the substrate on each side of the stacked gate structure. The high stress material layers are disposed on the substrate to cover the doped regions. The high stress material layers can increase the mobility of the carriers in the doped regions and hence accelerate the operating speed of the device.Type: ApplicationFiled: January 18, 2006Publication date: July 19, 2007Inventors: Kuan-Po Chen, Mu-Yi Liu
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Publication number: 20070158741Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.Type: ApplicationFiled: March 12, 2007Publication date: July 12, 2007Applicant: Macronix International Co., LtdInventors: Chia-Lun Hsu, Mu-Yi Liu, Tao-Cheng Lu, Ichen Yang, Kuan-Po Chen
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Patent number: 7192834Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.Type: GrantFiled: February 23, 2005Date of Patent: March 20, 2007Assignee: Macronix International Co., LtdInventors: Chia-Lun Hsu, Mu-Yi Liu, Tao-Cheng Liu, Ichen Yang, Kuan-Po Chen
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Publication number: 20060189081Abstract: A lateral double diffused metal oxide semiconductor (LDMOS) device, and method of fabricating such a device, are provided. The method comprises the steps of: (a) providing a substrate of a first conductivity type; (b) forming within the substrate a well region of a second conductivity type, the well region having a super steep retrograde (SSR) well profile in which a doping concentration changes with depth so as to provide a lighter doping concentration in a surface region of the well region than in a region below the surface region of the well region; (c) forming a gate layer which partly overlies the well region and is insulated from the well region; and (d) forming one of a source region and a drain region in the well region. The presence of the SSR well region provides a lighter surface doping to enable a higher breakdown voltage to be obtained within the LDMOS device, and heavier sub-surface doping to decrease the on-resistance.Type: ApplicationFiled: February 23, 2005Publication date: August 24, 2006Applicant: Macronix International Co., LtdInventors: Chia-Lun Hsu, Mu-Yi Liu, Tao-Cheng Lu, Ichen Yang, Kuan-Po Chen
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Publication number: 20060017102Abstract: An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased whilst maintaining a high breakdown voltage.Type: ApplicationFiled: April 7, 2005Publication date: January 26, 2006Applicant: Macronix International Co., Ltd.Inventors: Mu-Yi Liu, Chia-Lun Hsu, Ichen Yang, Kuan-Po Chen, Tao-Cheng Lu