Patents by Inventor Kuan-Ti Wang

Kuan-Ti Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11488870
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: November 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tien-Yu Hsieh, Kuan-Ti Wang, Han-Chen Chen, Kun-Hsien Lee
  • Publication number: 20210287942
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.
    Type: Application
    Filed: April 8, 2020
    Publication date: September 16, 2021
    Inventors: Tien-Yu Hsieh, Kuan-Ti Wang, Han-Chen Chen, Kun-Hsien Lee
  • Patent number: 9978745
    Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: May 22, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Ti Wang, Ling-Chun Chou, Kun-Hsien Lee
  • Publication number: 20180068998
    Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.
    Type: Application
    Filed: October 11, 2016
    Publication date: March 8, 2018
    Inventors: Kuan-Ti Wang, Ling-Chun Chou, Kun-Hsien Lee
  • Patent number: 9853021
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a shallow trench isolation (STI) adjacent to the first fin-shaped structure; and forming a gate structure on the first fin-shaped structure and the STI. Preferably, the gate structure comprises a left portion and the right portion and the work functions in the left portion and the right portion are different.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: December 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Ti Wang, Ling-Chun Chou, Kun-Hsien Lee