Patents by Inventor Kuan-Ting Liu
Kuan-Ting Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12382691Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.Type: GrantFiled: May 20, 2024Date of Patent: August 5, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang, Kuan-Ting Liu, Tzer-Min Shen, Chung-Wei Wu, Zhiqiang Wu
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Patent number: 12370657Abstract: A hex wrench includes a first wrench body having a first end face, a first slot, a second slot, six first faces, a guide angle, and six first corners, and a second wrench body having a second end face, a first block, and a second block. The first block has two ends each provided with two second faces aligning with two of the first faces. Each of the two ends of the first block is provided with a second corner aligning with one of the first corners. A third corner is formed between one of the two second faces and the second end face and aligns with the guide angle. The second block has two ends each provided with a third face. A fourth corner is formed between the third face and the second end face and aligns with the guide angle.Type: GrantFiled: February 21, 2023Date of Patent: July 29, 2025Assignee: NINGBO KING MOUNT CO., LTD.Inventor: Kuan-Ting Liu
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Patent number: 12336244Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.Type: GrantFiled: June 7, 2022Date of Patent: June 17, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Wei-Cheng Wang, Chia-Wei Chen, Jian-Hao Chen, Kuan-Ting Liu, Chi On Chui
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Publication number: 20250157851Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 seem to approximately 90 seem in a chamber pressure of approximately 1 Torr to approximately 100 Torr.Type: ApplicationFiled: February 13, 2023Publication date: May 15, 2025Inventors: He REN, Houssam LAZKANI, Raman GAIRE, Mehul NAIK, Kuan-Ting LIU
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Patent number: 12288811Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming an n-type work function layer in a gate trench in a gate structure, wherein the n-type work function layer is formed around first channel layers in a p-type gate region and around second channel layers in an n-type gate region, forming a first metal fill layer in a first gate trench over the n-type work function layer in the p-type gate region and in a second gate trench over the n-type work function layer in the n-type gate region, removing the first metal fill layer from the p-type gate region, removing the n-type work function layer from the p-type gate region, forming a p-type work function layer in the first gate trench of the p-type gate region, and forming a second metal fill layer in the first gate trench of the p-type gate region.Type: GrantFiled: May 6, 2022Date of Patent: April 29, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hang Chiu, Kuan-Ting Liu, Chi On Chui, Chia-Wei Chen, Jian-Hao Chen, Cheng-Lung Hung
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Patent number: 12237149Abstract: Embodiments of the present disclosure generally relate to a system used in a semiconductor device manufacturing process. More specifically, embodiments provided herein generally include apparatus and methods for synchronizing and controlling the delivery of an RF bias signal and a pulsed voltage waveform to one or more electrodes within a plasma processing chamber. The apparatus and methods disclosed herein can be useful to at least minimize or eliminate a microloading effect created while processing small dimension features that have differing densities across various regions of a substrate. The plasma processing methods and apparatus described herein are configured to improve the control of various characteristics of the generated plasma and control an ion energy distribution (IED) of the plasma generated ions that interact with a surface of a substrate during plasma processing.Type: GrantFiled: November 10, 2022Date of Patent: February 25, 2025Assignee: Applied Materials, Inc.Inventors: Deyang Li, Sunil Srinivasan, Yi-Chuan Chou, Shahid Rauf, Kuan-Ting Liu, Jason A. Kenney, Chung Liu, Olivier P. Joubert, Shreeram Jyoti Dash, Aaron Eppler, Michael Thomas Nichols
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Patent number: 12176251Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.Type: GrantFiled: July 25, 2023Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
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Publication number: 20240420948Abstract: Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.Type: ApplicationFiled: August 27, 2024Publication date: December 19, 2024Applicant: Applied Materials, Inc.Inventors: Abhijeet S. Bagal, Qian Fu, Kuan-Ting Liu, Chung Liu
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Patent number: 12170280Abstract: A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.Type: GrantFiled: November 29, 2023Date of Patent: December 17, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ji-Cheng Chen, Ching-Hwanq Su, Kuan-Ting Liu, Shih-Hang Chiu
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Patent number: 12148810Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.Type: GrantFiled: January 13, 2023Date of Patent: November 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
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Publication number: 20240379796Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
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Publication number: 20240379810Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
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Patent number: 12142531Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.Type: GrantFiled: May 2, 2022Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yen Tsai, Chung-Chiang Wu, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee, Ching-Hwanq Su, Yin-Chuan Chuang, Kuan-Ting Liu
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Patent number: 12125699Abstract: Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.Type: GrantFiled: June 28, 2021Date of Patent: October 22, 2024Assignee: Applied Materials, Inc.Inventors: Abhijeet S. Bagal, Qian Fu, Kuan-Ting Liu, Chung Liu
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Publication number: 20240313067Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.Type: ApplicationFiled: May 20, 2024Publication date: September 19, 2024Inventors: Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang, Kuan-Ting Liu, Tzer-Min Shen, Chung-Wei Wu, Zhiqiang Wu
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Patent number: 12094948Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.Type: GrantFiled: September 3, 2021Date of Patent: September 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
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Patent number: 12076849Abstract: A hex wrench holder structure includes a tool holder having a first face, a second face, a third face, a fourth face, a fifth face, and a sixth face. The first face is provided with multiple first receiving grooves and multiple first mounting portions aligning with the first receiving grooves respectively. The second face is provided with multiple second receiving grooves. The third face is provided with multiple third receiving grooves. The fourth face is provided with multiple second mounting portions aligning with the second receiving grooves respectively. The fifth face is provided with multiple third mounting portions aligning with the third receiving grooves respectively.Type: GrantFiled: December 21, 2022Date of Patent: September 3, 2024Assignee: NINGBO KING MOUNT CO., LTD.Inventor: Kuan-Ting Liu
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Publication number: 20240278397Abstract: A hex wrench includes a first wrench body having a first end face, a first slot, a second slot, six first faces, a guide angle, and six first corners, and a second wrench body having a second end face, a first block, and a second block. The first block has two ends each provided with two second faces aligning with two of the first faces. Each of the two ends of the first block is provided with a second corner aligning with one of the first corners. A third corner is formed between one of the two second faces and the second end face and aligns with the guide angle. The second block has two ends each provided with a third face. A fourth corner is formed between the third face and the second end face and aligns with the guide angle.Type: ApplicationFiled: February 21, 2023Publication date: August 22, 2024Inventor: Kuan-Ting Liu
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Patent number: 12023796Abstract: A tool box assembly includes at least one case, at least one tool holder mounted in and rotated relative to the at least one case, and multiple hand tools mounted in the at least one tool holder. The at least one case has a first pivot portion and multiple locking elements. Each of the locking elements has a second pivot portion, a connecting portion, and a press portion. The at least one tool holder has a third pivot portion. When the press portion is pressed, each of the locking elements is rotated about the connecting portion, so that the third pivot portion is detached from the second pivot portion, and the at least one tool holder is detached from the at least one case. Thus, the at least one tool holder and the hand tools are used individually.Type: GrantFiled: October 17, 2022Date of Patent: July 2, 2024Assignee: NINGBO KING MOUNT CO., LTD.Inventor: Kuan-Ting Liu
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Publication number: 20240208038Abstract: A hex wrench holder structure includes a tool holder having a first face, a second face, a third face, a fourth face, a fifth face, and a sixth face. The first face is provided with multiple first receiving grooves and multiple first mounting portions aligning with the first receiving grooves respectively. The second face is provided with multiple second receiving grooves. The third face is provided with multiple third receiving grooves. The fourth face is provided with multiple second mounting portions aligning with the second receiving grooves respectively. The fifth face is provided with multiple third mounting portions aligning with the third receiving grooves respectively.Type: ApplicationFiled: December 21, 2022Publication date: June 27, 2024Inventor: Kuan-Ting Liu