Abstract: A network switch can include a precision time protocol (PTP) module and a circuit board. The PTP module can provide a first clock signal and include a predetermined interface. The circuit board can include a socket, an oscillator and a selection unit. The socket can be inserted by the predetermined interface to receive the first clock signal. The oscillator can provide a second clock signal. The selection unit can include a first terminal, a second terminal, an output terminal and a selection terminal. The first terminal can receive the first clock signal when the predetermined interface is inserted into the socket. The second terminal can receive the second clock signal. The output terminal can output one of the first clock signal and the second clock signal. The selection terminal can receive a selection signal to control the output terminal to output the first clock signal or the second clock signal.

Abstract: A network switch includes a circuit board and a plurality of transmission ports. The circuit board is disposed in a chassis, and an opening of the chassis is corresponding to a first reference line. The plurality of transmission ports are disposed on an edge of the circuit board. The edge is corresponding to a second reference line, and the first reference line and the second reference line form an acute angle.

Abstract: A network system includes P upper switches, Q lower switches, and a first mapping device. Each upper switch of the P upper switches includes a plurality of upper ports. A group of upper switches selected from the P upper switches includes P1 upper switches. Each lower switch of the Q lower switches includes a plurality of upper ports. The first mapping device includes P1 upper adapter terminals coupled to a part of upper ports of the P1 upper switches, and P1 lower adapter terminals coupled to lower ports of a part of Q lower switches. The first mapping device is used for allocating a plurality of transmitting channels and receiving channels received by each upper adapter terminal to the P1 lower adapter terminals.