Patents by Inventor Kuan-Wei Chuang
Kuan-Wei Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250062185Abstract: An electronic package and a manufacturing method thereof are provided, in which an offset suppression layer is formed on a carrier, a first electronic element and a second electronic element are respectively disposed on the offset suppression layer, and an encapsulant is formed on the offset suppression layer to respectively cover the first electronic element and the second electronic element. The offset suppression layer effectively suppresses or prevents possible offset caused by the encapsulant to the first electronic element and the second electronic element, thereby avoiding yield loss of the semiconductor package.Type: ApplicationFiled: December 13, 2023Publication date: February 20, 2025Inventors: Yi-Ling CHEN, Kuan-Wei CHUANG
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Publication number: 20240258121Abstract: An electronic structure is provided, in which a plurality of conductors are disposed on one surface of an electronic body, an epoxy molding compound is used as a protective layer to encapsulate the plurality of conductors, a circuit portion is bonded onto the other surface of the electronic body, and a plurality of external bumps and solder material are formed on the circuit portion. Therefore, with the design of the protective layer, heat energy can be effectively transferred from the protective layer to the solder material below during a process of heating the electronic structure so as to avoid a problem of non-wetting of the solder material.Type: ApplicationFiled: May 1, 2023Publication date: August 1, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yi-Ling CHEN, Kuan-Wei CHUANG
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Patent number: 9548220Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: GrantFiled: January 4, 2016Date of Patent: January 17, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Publication number: 20160118271Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: ApplicationFiled: January 4, 2016Publication date: April 28, 2016Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Publication number: 20160079110Abstract: A semiconductor package is provided, which includes: a carrier; a frame having a plurality of openings, wherein the frame is bonded to the carrier and made of a material different from that of the carrier; a plurality of electronic elements disposed in the openings of the frame, respectively; an encapsulant formed in the openings of the frame for encapsulating the electronic elements; and a circuit layer formed on and electrically connected to the electronic elements. By accurately controlling the size of the openings of the frame, the present invention increases the accuracy of positioning of the electronic elements so as to improve the product yield in subsequent processes.Type: ApplicationFiled: September 10, 2015Publication date: March 17, 2016Inventors: Kuan-Wei Chuang, Shih-Kuang Chiu, Chun-Tang Lin, Jung-Pang Huang
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Patent number: 9257381Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: GrantFiled: December 20, 2012Date of Patent: February 9, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Patent number: 8895367Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.Type: GrantFiled: August 12, 2013Date of Patent: November 25, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
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Publication number: 20140127864Abstract: A method of fabricating a semiconductor package is provided, including providing an interposer having a plurality of conductive elements, disposing the interposer on a carrier having a plurality of recessed portions for the conductive elements to be received therein such that the interposer is coupled to the carrier, attaching the semiconductor element to the interposer, and removing the carrier. Coupling the interposer to the carrier prevents the conductive elements from displacement under pressure. Therefore, the conductive elements will not be in poor or no electrical contact with the interposer.Type: ApplicationFiled: December 28, 2012Publication date: May 8, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Che Lai
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Publication number: 20140077387Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: cutting a substrate into a plurality of interposers; disposing the interposers on a carrier, wherein the interposers are spaced from one another by a distance; disposing at least a semiconductor element on each of the interposers; forming an encapsulant to encapsulate the interposers and the semiconductor elements; and removing the carrier. Therefore, by cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: ApplicationFiled: November 20, 2012Publication date: March 20, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi Che Lai
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Publication number: 20140070424Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.Type: ApplicationFiled: December 20, 2012Publication date: March 13, 2014Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Kuan-Wei Chuang, Chun-Tang Lin, Yi-Chian Liao, Yi-Che Lai
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Publication number: 20130330883Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.Type: ApplicationFiled: August 12, 2013Publication date: December 12, 2013Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
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Patent number: 8519526Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.Type: GrantFiled: May 20, 2011Date of Patent: August 27, 2013Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
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Publication number: 20120161301Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.Type: ApplicationFiled: May 20, 2011Publication date: June 28, 2012Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang