Patents by Inventor Kuan-Wei SU

Kuan-Wei SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11892409
    Abstract: The present invention includes a shell, a light emitter, a beam splitter, a convergent lens, an optical filter, a collimation unit, a discrete light detection unit, and a processing unit. The shell includes a sample well to contain a sample. The light emitter generates a detection beam towards the beam splitter, the detection beam is reflected by the beam splitter before being converged by the convergent lens onto the sample, and a Raman scattered beam is scattered from the sample. The Raman scattered beam respectively passes through the convergent lens, the beam splitter, the optical filter, and the collimation unit, allowing the collimation unit to collimate the Raman scattered beam into a collimated beam. The discrete light detection unit generates multiple light intensity signals according to the collimated beam received, and the processing unit generates a detection result according to the light intensity signals to help detect toxins.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: February 6, 2024
    Assignee: Taiwan RedEye Biomedical Inc.
    Inventors: Tsung-Jui Lin, Shuo-Ting Yan, Kuan-Wei Su
  • Publication number: 20230343640
    Abstract: A method for forming a conductive feature includes following operations. A first insulating layer is formed over a substrate. The first insulating layer is patterned to form a first recess in the first insulating layer. The first recess is filled with a conductive material. A plurality of second recesses are formed in the conductive material. Each of the second recesses overlaps the first recess. A portion of the conductive material is removed to form a first conductive feature. A ratio of a sum of opening areas of the second recesses to an opening area of the first recess is less than 1%.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 26, 2023
    Inventors: KUAN WEI SU, CHE-LI LIN, LING-SUNG WANG, LI-YI CHEN
  • Publication number: 20230223480
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.
    Type: Application
    Filed: February 27, 2023
    Publication date: July 13, 2023
    Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, Chia-Wei LEE, Kuan-Wei SU, Chia-Ming PAN
  • Publication number: 20230064914
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, Chia-Wei LEE, Kuan-Wei SU, Chia-Ming PAN
  • Publication number: 20230065897
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Yu-Chu LIN, Wen-Chih CHIANG, Chi-Chung JEN, Ming-Hong SU, Mei-Chen SU, C.W. LEE, Kuan-Wei SU, Chia-Ming PAN
  • Patent number: 11594645
    Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Wen-Chih Chiang, Chi-Chung Jen, Ming-Hong Su, Mei-Chen Su, Chia-Wei Lee, Kuan-Wei Su, Chia-Ming Pan
  • Publication number: 20220369980
    Abstract: A sanitary device for the urine glucose test includes a urine container formed on an inner wall of a main body, and a measuring module with an inner space mounted at a bottom of the urine container. Within the inner space, a lens attaches to the bottom of the urine container, a rail faces a bottom surface of the lens, and a driving module moves a light unit shooting a detection beam to a measuring surface of the lens along the rail. The measuring surface contacts urine in the urine container, and reflects the detection beam out of the bottom surface into a sensor. The sensor is electrically connected to a processor. The processor determines a urine glucose level and generates a urine glucose level data instantly from an angle of incidence of the detection beam on the measuring surface and from a beam intensity signal from the sensor.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 24, 2022
    Inventors: Shuo-Ting YAN, Tsung-Jui LIN, Yu-Hsun CHEN, Kuan-Wei SU
  • Patent number: 11257719
    Abstract: Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Wei Su, Chun Yu Huang, Chih-Hsun Lin, Ping-Pang Hsieh
  • Patent number: 11243216
    Abstract: A hemoglobin detecting method is executed by a mobile device having a hemoglobin detecting function. The mobile device includes a processor unit, a first light source that generates a first light beam, and a light detecting module that receives a second light beam that is generated when the first light beam travels through an analyte solution and is reflected. The light detecting module generates first to fourth intensity signals according to the second light beam, and the processor unit determines whether the absorption spectrum of the analyte solution matches a target spectrum. If the absorption spectrum of the analyte solution matches the target spectrum, the processor unit generates positive result information; otherwise, the processor unit generates negative result information. The mobile device provides a fast and accurate way to detect blood in a stool solution, which does not require collecting samples of stool or applying any chemical.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: February 8, 2022
    Assignee: Taiwan Redeye Biomedical Inc.
    Inventors: Shuo-Ting Yan, Kuan-Wei Su, I-Hua Wang, Chen-Chung Chang
  • Publication number: 20200355702
    Abstract: A hemoglobin detecting method is executed by a mobile device having a hemoglobin detecting function. The mobile device includes a processor unit, a first light source that generates a first light beam, and a light detecting module that receives a second light beam that is generated when the first light beam travels through an analyte solution and is reflected. The light detecting module generates first to fourth intensity signals according to the second light beam, and the processor unit determines whether the absorption spectrum of the analyte solution matches a target spectrum. If the absorption spectrum of the analyte solution matches the target spectrum, the processor unit generates positive result information; otherwise, the processor unit generates negative result information. The mobile device provides a fast and accurate way to detect blood in a stool solution, which does not require collecting samples of stool or applying any chemical.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 12, 2020
    Inventors: SHUO-TING YAN, KUAN-WEI SU, I-HUA WANG, CHEN-CHUNG CHANG
  • Patent number: 10823665
    Abstract: The invention provides a smart toilet seat having an occult blood detecting module, the occult blood detecting module further including: a case, a power unit, a light source, a photo sensor, and a first processor; wherein the occult blood detecting module being able to be lowered to slightly above water seal inside a toilet; the light source emitting the emitted light onto an excrement solution below surface of the water seal, the photo sensor receiving a reflected light reflected by the excrement solution and the toilet to generate a detection signal; the first processor receiving and processing the detection signal from the photo sensor to generate a detection result. Alternatively, the case includes an extension section disposed with a reflector and a filter, which can be lowered below the water seal for detection.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 3, 2020
    Assignee: TAIWAN REDEYE BIOMEDICAL INC.
    Inventors: Shuo-Ting Yan, Kuan-Wei Su, Chen-Chung Chang, I-Hua Wang
  • Publication number: 20200294862
    Abstract: Integrated circuit devices having improved interlayer dielectric (ILD) layer topography and methods of fabrication thereof are disclosed herein. An exemplary integrated circuit device includes a first gate structure having a first height disposed over a substrate in a first region and a second gate structure having a second height disposed over the substrate in a second region. The second height is less than the first height. A first contact etch stop layer is disposed over the first gate structure. A second contact etch stop layer disposed over the second gate structure. The first contact etch stop layer has a first thickness, the second contact etch stop layer has a second thickness, and the second thickness is greater than the first thickness. An interlayer dielectric layer is disposed over the first contact etch stop layer and the second contact etch stop layer.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Kuan-Wei Su, Chun Yu Huang, Chih-Hsun Lin, Ping-Pang Hsieh
  • Patent number: 10746652
    Abstract: A hemoglobin sensor capable of quickly detecting occult blood of excreta in a toilet and a detecting method thereof are disclosed. The hemoglobin sensor includes a handheld housing and a result presentation unit. The housing includes a light emitting unit, an operating interface, a light sensing unit, and a data processor disposed therein. The operating interface is connected to the light emitting unit for activating the light emitting unit to emit a plurality of incident light beams having wavelengths in a range between 350 nm and 800 nm. The incident light beams penetrate a solution in a container having excreta and hit a light reflector of the container to produce at least one detection light beam. The light sensing unit receives the detection light beam and output a detection signal, and the data processor generates a detection result data after receiving the detection signal and analyzing it.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 18, 2020
    Assignee: REDEYE INC.
    Inventors: Shuo-Ting Yan, Kuan-Wei Su, I-Hua Wang, Chen-Chung Chang
  • Patent number: 10699960
    Abstract: Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Wei Su, Chun Yu Huang, Chih-Hsun Lin, Ping-Pang Hsieh
  • Patent number: 10672777
    Abstract: A method for manufacturing a semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively formed on the silicon substrate and connected to each other. A limiting block is formed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer is formed to blanketly cover the first structure, the second structure and the limiting block, in which the BARC layer includes a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are formed on the external surface of the BARC layer.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Wei Su, Yung-Lung Hsu, Chih-Hsun Lin, Kun-Tsang Chuang, Chiang-Ming Chuang, Chia-Yi Tseng
  • Publication number: 20200150030
    Abstract: The invention provides a smart toilet seat having an occult blood detecting module, the occult blood detecting module further including: a case, a power unit, a light source, a photo sensor, and a first processor; wherein the occult blood detecting module being able to be lowered to slightly above water seal inside a toilet; the light source emitting the emitted light onto an excrement solution below surface of the water seal, the photo sensor receiving a reflected light reflected by the excrement solution and the toilet to generate a detection signal; the first processor receiving and processing the detection signal from the photo sensor to generate a detection result. Alternatively, the case includes an extension section disposed with a reflector and a filter, which can be lowered below the water seal for detection.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 14, 2020
    Inventors: Shuo-Ting YAN, Kuan-Wei SU, Chen-Chung CHANG, I-Hua WANG
  • Publication number: 20200006152
    Abstract: Methods for improving interlayer dielectric (ILD) layer topography and resulting integrated circuit devices are disclosed herein. An exemplary method includes forming a first contact etch stop layer having a first thickness over a first region of a wafer, forming a second contact etch stop layer having a second thickness over a second region of the wafer, and forming an ILD layer over the first contact etch stop layer and the second contact etch stop layer. A first topography variation exists between the first region and the second region. The second thickness is different than the first thickness to achieve a second topography variation that is less than the first topography variation. The first topography variation can be caused by a height difference between a first gate structure disposed over the wafer in the first region and a second gate structure disposed over the wafer in the second region.
    Type: Application
    Filed: August 30, 2018
    Publication date: January 2, 2020
    Inventors: Kuan-Wei Su, Chun Yu Huang, Chih-Hsun Lin, Ping-Pang Hsieh
  • Publication number: 20190181149
    Abstract: A method for manufacturing a semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively formed on the silicon substrate and connected to each other. A limiting block is formed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer is formed to blanketly cover the first structure, the second structure and the limiting block, in which the BARC layer includes a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are formed on the external surface of the BARC layer.
    Type: Application
    Filed: February 18, 2019
    Publication date: June 13, 2019
    Inventors: Kuan-Wei SU, Yung-Lung HSU, Chih-Hsun LIN, Kun-Tsang CHUANG, Chiang-Ming CHUANG, Chia-Yi TSENG
  • Patent number: 10211214
    Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively disposed on the silicon substrate and connected to each other. A limiting block is disposed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer blanketly covering the first structure, the second structure and the limiting block, in which the BARC layer comprises a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are disposed on the external surface of the BARC layer.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: February 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Wei Su, Yung-Lung Hsu, Chih-Hsun Lin, Kun-Tsang Chuang, Chiang-Ming Chuang, Chia-Yi Tseng
  • Publication number: 20180261609
    Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively disposed on the silicon substrate and connected to each other. A limiting block is disposed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer blanketly covering the first structure, the second structure and the limiting block, in which the BARC layer comprises a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are disposed on the external surface of the BARC layer.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 13, 2018
    Inventors: Kuan-Wei SU, Yung-Lung HSU, Chih-Hsun LIN, Kun-Tsang CHUANG, Chiang-Ming CHUANG, Chia-Yi TSENG