Patents by Inventor Kuan-Wun LIN
Kuan-Wun LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250234565Abstract: A device includes a semiconductor substrate, an interfacial layer, a high-k dielectric layer, a first electrode, and a second electrode. The interfacial layer is over the semiconductor substrate. The high-k dielectric layer is over the interfacial layer. The first electrode is over the high-k dielectric layer. The second electrode is over the interfacial layer. The first electrode laterally surrounds the second electrode in a top view.Type: ApplicationFiled: March 4, 2025Publication date: July 17, 2025Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN
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Patent number: 12274078Abstract: A memory device includes a semiconductor substrate and a memory cell at a memory region of the semiconductor substrate. A memory cell includes a memory portion of the semiconductor substrate, a tunneling layer, a storage layer, a first electrode, and a second electrode. The tunneling layer is over the memory portion of the semiconductor substrate. The storage layer is over and in contact with the tunneling layer. The first electrode is over the storage layer. The second electrode is over and in contact with the tunneling layer but is spaced apart from the storage layer.Type: GrantFiled: February 2, 2023Date of Patent: April 8, 2025Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jenn-Gwo Hwu, Bo-Jyun Chen, Kuan-Wun Lin
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Publication number: 20230189539Abstract: A memory device includes a semiconductor substrate and a memory cell at a memory region of the semiconductor substrate. A memory cell includes a memory portion of the semiconductor substrate, a tunneling layer, a storage layer, a first electrode, and a second electrode. The tunneling layer is over the memory portion of the semiconductor substrate. The storage layer is over and in contact with the tunneling layer. The first electrode is over the storage layer. The second electrode is over and in contact with the tunneling layer but is spaced apart from the storage layer.Type: ApplicationFiled: February 2, 2023Publication date: June 15, 2023Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN
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Patent number: 11574908Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.Type: GrantFiled: December 3, 2021Date of Patent: February 7, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jenn-Gwo Hwu, Bo-Jyun Chen, Kuan-Wun Lin
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Publication number: 20220093601Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.Type: ApplicationFiled: December 3, 2021Publication date: March 24, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN
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Patent number: 11195835Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.Type: GrantFiled: December 26, 2019Date of Patent: December 7, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jenn-Gwo Hwu, Bo-Jyun Chen, Kuan-Wun Lin
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Publication number: 20210202484Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.Type: ApplicationFiled: December 26, 2019Publication date: July 1, 2021Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Jenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN