Patents by Inventor Kuan-Wun LIN

Kuan-Wun LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250234565
    Abstract: A device includes a semiconductor substrate, an interfacial layer, a high-k dielectric layer, a first electrode, and a second electrode. The interfacial layer is over the semiconductor substrate. The high-k dielectric layer is over the interfacial layer. The first electrode is over the high-k dielectric layer. The second electrode is over the interfacial layer. The first electrode laterally surrounds the second electrode in a top view.
    Type: Application
    Filed: March 4, 2025
    Publication date: July 17, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN
  • Patent number: 12274078
    Abstract: A memory device includes a semiconductor substrate and a memory cell at a memory region of the semiconductor substrate. A memory cell includes a memory portion of the semiconductor substrate, a tunneling layer, a storage layer, a first electrode, and a second electrode. The tunneling layer is over the memory portion of the semiconductor substrate. The storage layer is over and in contact with the tunneling layer. The first electrode is over the storage layer. The second electrode is over and in contact with the tunneling layer but is spaced apart from the storage layer.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: April 8, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Bo-Jyun Chen, Kuan-Wun Lin
  • Publication number: 20230189539
    Abstract: A memory device includes a semiconductor substrate and a memory cell at a memory region of the semiconductor substrate. A memory cell includes a memory portion of the semiconductor substrate, a tunneling layer, a storage layer, a first electrode, and a second electrode. The tunneling layer is over the memory portion of the semiconductor substrate. The storage layer is over and in contact with the tunneling layer. The first electrode is over the storage layer. The second electrode is over and in contact with the tunneling layer but is spaced apart from the storage layer.
    Type: Application
    Filed: February 2, 2023
    Publication date: June 15, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN
  • Patent number: 11574908
    Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: February 7, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Bo-Jyun Chen, Kuan-Wun Lin
  • Publication number: 20220093601
    Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN
  • Patent number: 11195835
    Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: December 7, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Bo-Jyun Chen, Kuan-Wun Lin
  • Publication number: 20210202484
    Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo HWU, Bo-Jyun CHEN, Kuan-Wun LIN