Patents by Inventor Kuan-Yang Liao
Kuan-Yang Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7595234Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.Type: GrantFiled: September 15, 2006Date of Patent: September 29, 2009Assignee: United Microelectronics Corp.Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen, Yi-Yiing Chiang, Yu-Lan Chang, Chung-Ju Lee, Chih-Ning Wu, Kuan-Yang Liao
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Patent number: 7462542Abstract: A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.Type: GrantFiled: November 7, 2007Date of Patent: December 9, 2008Assignee: United Microelectronics Corp.Inventors: Alex Liu, Cheng-Tung Huang, Wei-Tsun Shiau, Kuan-Yang Liao
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Publication number: 20080057655Abstract: A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.Type: ApplicationFiled: November 7, 2007Publication date: March 6, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Alex Liu, Cheng-Tung Huang, Wei-Tsun Shiau, Kuan-Yang Liao
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Patent number: 7326622Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.Type: GrantFiled: November 8, 2005Date of Patent: February 5, 2008Assignee: United Microelectronics Corp.Inventors: Yi-Cheng Liu, Jiunn-Ren Hwang, Wei-Tsun Shiau, Cheng-Tung Huang, Kuan-Yang Liao
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Patent number: 7319063Abstract: The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.Type: GrantFiled: February 2, 2005Date of Patent: January 15, 2008Assignee: United Microelectronics Corp.Inventors: Wen-Shiang Liao, Wei-Tsun Shiau, Kuan-Yang Liao
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Publication number: 20070126032Abstract: The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.Type: ApplicationFiled: February 12, 2007Publication date: June 7, 2007Inventors: WEN-SHIANG LIAO, Wei-Tsun Shiau, Kuan-Yang Liao
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Patent number: 7220647Abstract: A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer sequentially stacked over the substrate. The method includes cleaning the substrate with phosphoric acid solution and hydrofluoric acid solution so that silicon nitride residues formed in a reaction between the nitrogen-containing barrier layer and the silicon-containing gate layer can be removed and the amount of pollutants and particles can be reduced. Ultimately, the yield of the process as well as the quality and reliability of the device are improved.Type: GrantFiled: February 2, 2005Date of Patent: May 22, 2007Assignee: United Microelectronics Corp.Inventors: Chih-Ning Wu, Charlie C J Lee, Kuan-Yang Liao
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Patent number: 7214988Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.Type: GrantFiled: September 20, 2005Date of Patent: May 8, 2007Assignee: United Microelectronics Corp.Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen, Yi-Yiing Chiang, Yu-Lan Chang, Chung-Ju Lee, Chih-Ning Wu, Kuan-Yang Liao
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Patent number: 7196019Abstract: A method of removing spacers after forming a MOS transistor on a wafer. The MOS transistor comprises a gate disposed on the substrate, spacers disposed on the sidewalls of the gate and a source and a drain region in the substrate beside the spacers. The spacers are removed by performing a wet etching process in the dark such that during the spacer removal process, the source and the drain region in a MOS transistor can be prevented from damages.Type: GrantFiled: December 21, 2004Date of Patent: March 27, 2007Assignee: United Microelectronics Corp.Inventors: Chih-Ning Wu, Charlie C J Lee, Kuan-Yang Liao
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Publication number: 20070066041Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.Type: ApplicationFiled: September 15, 2006Publication date: March 22, 2007Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen, Yi-Yiing Chiang, Yu-Lan Chang, Chung-Ju Lee, Chih-Ning Wu, Kuan-Yang Liao
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Publication number: 20070063290Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.Type: ApplicationFiled: September 20, 2005Publication date: March 22, 2007Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen, Yi-Yiing Chiang, Yu-Lan Chang, Chung-Ju Lee, Chih-Ning Wu, Kuan-Yang Liao
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Patent number: 7135365Abstract: First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.Type: GrantFiled: March 30, 2005Date of Patent: November 14, 2006Assignee: United Microelectronics Corp.Inventors: Yi-Cheng Liu, Wen-Chi Chen, Tzu-Yun Chang, Bang-Chiang Lan, Cheng-Tung Huang, Wei-Tsun Shiau, Kuan-Yang Liao
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Publication number: 20060228843Abstract: A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.Type: ApplicationFiled: April 12, 2005Publication date: October 12, 2006Inventors: Alex Liu, Cheng-Tung Huang, Wei-Tsun Shiau, Kuan-Yang Liao
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Publication number: 20060228847Abstract: First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.Type: ApplicationFiled: March 30, 2005Publication date: October 12, 2006Inventors: Yi-Cheng Liu, Wen-Chi Chen, Tzu-Yun Chang, Bang-Chiang Lan, Cheng-Tung Huang, Wei-Tsun Shiau, Kuan-Yang Liao
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Publication number: 20060172476Abstract: The invention is directed to a method for manufacturing a fin field effect transistor including a fully silicidated gate electrode. The method is suitable for a substrate including a fin structure, a straddle gate, a source/drain region and a dielectric layer formed thereon, wherein the straddle gate straddles over the fin structure, the source/drain region is located in a portion of the fin structure exposed by the straddle gate and the dielectric layer covers the substrate. The method includes steps of performing a planarization process to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed and performing a salicide process to convert the straddle gate into a fully silicidated gate electrode.Type: ApplicationFiled: February 2, 2005Publication date: August 3, 2006Inventors: Wen-Shiang Liao, Wei-Tsun Shiau, Kuan-Yang Liao
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Publication number: 20060172548Abstract: A method of cleaning a wafer, adapted for a patterned gate structure. The gate structures comprise a gate dielectric layer, a nitrogen-containing barrier layer and a silicon-containing gate layer sequentially stacked over the substrate. The method includes cleaning the substrate with phosphoric acid solution and hydrofluoric acid solution so that silicon nitride residues formed in a reaction between the nitrogen-containing barrier layer and the silicon-containing gate layer can be removed and the amount of pollutants and particles can be reduced. Ultimately, the yield of the process as well as the quality and reliability of the device are improved.Type: ApplicationFiled: February 2, 2005Publication date: August 3, 2006Inventors: Chih-Ning Wu, Charlie Lee, Kuan-Yang Liao
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Publication number: 20060134899Abstract: A method of removing spacers after forming a MOS transistor on a wafer. The MOS transistor comprises a gate disposed on the substrate, spacers disposed on the sidewalls of the gate and a source and a drain region in the substrate beside the spacers. The spacers are removed by performing a wet etching process in the dark such that during the spacer removal process, the source and the drain region in a MOS transistor can be prevented from damages.Type: ApplicationFiled: December 21, 2004Publication date: June 22, 2006Inventors: Chih-Ning Wu, Charlie CJ Lee, Kuan-Yang Liao
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Publication number: 20060110688Abstract: An etching process compatible with DUV lithography is described. A mask layer is previously formed over a material layer to be etched through a DUV lithography process of 193 nm or 157 nm. Then, plasma etching is performed to pattern the material layer using the mask layer as an etching mask, wherein the etching gas causes a protective layer to form on the surface of the mask layer. The etching gas of the plasma etching includes at least a halogen-containing gas and Xe, wherein the halogen can be F, Cl, Br or a combination thereof.Type: ApplicationFiled: November 19, 2004Publication date: May 25, 2006Inventors: Chung-Ju Lee, Chih-Ning Wu, Kuan-Yang Liao
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Publication number: 20060099763Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.Type: ApplicationFiled: October 28, 2004Publication date: May 11, 2006Inventors: Yi-Cheng Liu, Jiunn-Ren Hwang, Wei-Tsun Shiau, Cheng-Tung Huang, Kuan-Yang Liao
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Publication number: 20060094195Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.Type: ApplicationFiled: November 8, 2005Publication date: May 4, 2006Inventors: Yi-Cheng Liu, Jiunn-Ren Hwang, Wei-Tsun Shiau, Cheng-Tung Huang, Kuan-Yang Liao