Abstract: An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.

Abstract: An apparatus for characterizing capacitance and thickness of an insulating layer constructed between a conductive gate and a substrate has at least one test structure formed at a surface of a substrate. Each test structure has a bulk region formed of a semiconductor within the surface. Further the test structure has at least one source region and one drain region within the bulk region. A thin insulating layer is placed above the each source region, each drain region, and the bulk region. A conductive gate is placed above the thin insulating layer. A capacitance-voltage measuring device measures a capacitance value of the test structure, while forcing the bulk region between the source region and the drain region to be floating. An insulating layer thickness calculator determines the thickness of the insulating layer from the capacitance.

Abstract: A method of fabricating a CMOS device having (1) an anti-SCE block region below a channel region and (2) a metal gate. The invention uses a masking layer having an opening to define the anti-SCE block implant and also the gate structure. The method comprises forming a masking layer having a first opening defining a channel region over the substrate. In a key step, performing an Anti-SCE block implant to create an anti-SCE region. Next, a forming a gate dielectric layer is formed on the substrate in the first opening. A conductive layer is formed over the substrate in the channel region and over the masking layer. The conductive layer is planarized to form a metal gate metal. The barrier layer is removed. LDD regions are formed. Spacers are formed on the sidewall of the metal gate. Source/Drain regions are implanted adjacent to the metal gate stack.