Patents by Inventor Kuan Yee Woo

Kuan Yee Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8779566
    Abstract: In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: July 15, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Lee Han Meng @ Eugene Lee, Yien Sien Khoo, Kuan Yee Woo
  • Publication number: 20130045572
    Abstract: In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Lee Han Meng @ Eugene Lee, Yien Sien Khoo, Kuan Yee Woo
  • Patent number: 8304887
    Abstract: An integrated circuit package is described that includes a substrate, a leadframe and one or more integrated circuits that are positioned between the substrate and the leadframe. Multiple electrical components may be attached to one or both sides of the substrate. The active face of the integrated circuit is electrically and physically connected to the substrate. The back side of the integrated circuit is mounted on a die attach pad of the leadframe. The leadframe includes multiple leads that are physically attached to and electrically coupled with the substrate. A molding material encapsulates portions of the substrate, the leadframe and the integrated circuit. Methods for forming such packages are also described.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Lee Han Meng @ Eugene Lee, Kuan Yee Woo
  • Patent number: 8203199
    Abstract: A semiconductor chip package having multiple leadframes is disclosed. Packages can include a first leadframe having a first plurality of electrical leads and a die attach pad having a plurality of tie bars, a second leadframe generally parallel to the first leadframe and having a second plurality of electrical leads, and a mold or encapsulant. Tie bars can be located on three main sides of the die attach pad, but not the fourth main side. Gaps in the first and second plurality of electrical leads can be enlarged or aligned with each other to enable the elimination of mold flash outside the encapsulated region, which can be accomplished with mold cavity bar protrusions. Additional components can include a primary die, a secondary die, an inductor and/or a capacitor. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: June 19, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Lee Han Meng Eugene Lee, Kuan Yee Woo
  • Publication number: 20110140262
    Abstract: An integrated circuit package is described that includes a substrate, a leadframe and one or more integrated circuits that are positioned between the substrate and the leadframe. Multiple electrical components may be attached to one or both sides of the substrate. The active face of the integrated circuit is electrically and physically connected to the substrate. The back side of the integrated circuit is mounted on a die attach pad of the leadframe. The leadframe includes multiple leads that are physically attached to and electrically coupled with the substrate. A molding material encapsulates portions of the substrate, the leadframe and the integrated circuit. Methods for forming such packages are also described.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Lee Han Meng @ Eugene LEE, Kuan Yee WOO
  • Publication number: 20110140249
    Abstract: A semiconductor chip package having multiple leadframes is disclosed. Packages can include a first leadframe having a first plurality of electrical leads and a die attach pad having a plurality of tie bars, a second leadframe generally parallel to the first leadframe and having a second plurality of electrical leads, and a mold or encapsulant. Tie bars can be located on three main sides of the die attach pad, but not the fourth main side. Gaps in the first and second plurality of electrical leads can be enlarged or aligned with each other to enable the elimination of mold flash outside the encapsulated region, which can be accomplished with mold cavity bar protrusions. Additional components can include a primary die, a secondary die, an inductor and/or a capacitor. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Lee Han Meng Eugene LEE, Kuan Yee WOO