Abstract: A DC converter and a mode-switching method used in an electronic apparatus are included. The electronic apparatus includes a subsystem circuit. The DC power converter comprises a first voltage converting circuit electrically connected to the subsystem circuit, receiving a system voltage and a first reference voltage, and converting the system voltage to a first output voltage based on the first reference voltage; and a second voltage converting circuit electrically connected to the subsystem circuit and receiving the system voltage and a second reference voltage, and converting the system voltage to a second output voltage to the same output end of the first voltage converting circuit based on the second reference voltage; wherein the second voltage converting circuit outputs the second output voltage to the subsystem circuit when the first output voltage at the output end is smaller than a threshold.

Abstract: A voltage generating circuit for generating a plurality of associated voltages includes a constant current source for generating a constant current; a plurality of resistors connected in series to the constant current source in series for generating a plurality of associated reference voltages; and a first controlled switch connected to a first resistor in parallel, wherein the plurality of associated reference voltages are changed by optionally conducting the first controlled switch to control the flow of the constant current through the first resistor.

Abstract: A circuit and a method generate a power-on reset signal having a leading part and a trailing part. The circuit includes a startup circuit generating the leading part of the power-on reset signal and a second circuit generating the trailing part of the power-on reset signal. The power-on reset circuit is implemented by a process which does not rely on native devices having zero threshold voltage to control a circuit generating the trailing part of the power-on reset signal.

Abstract: A voltage generating circuit for generating a plurality of associated voltages includes a constant current source for generating a constant current; a plurality of resistors connected in series to the constant current source in series for generating a plurality of associated reference voltages; and a first controlled switch connected to a first resistor in parallel, wherein the plurality of associated reference voltages are changed by optionally conducting the first controlled switch to control the flow of the constant current through the first resistor.

Abstract: A DC converter and a mode-switching method used in an electronic apparatus are included. The electronic apparatus includes a subsystem circuit. The DC power converter comprises a first voltage converting circuit electrically connected to the subsystem circuit, receiving a system voltage and a first reference voltage, and converting the system voltage to a first output voltage based on the first reference voltage; and a second voltage converting circuit electrically connected to the subsystem circuit and receiving the system voltage and a second reference voltage, and converting the system voltage to a second output voltage to the same output end of the first voltage converting circuit based on the second reference voltage; wherein the second voltage converting circuit outputs the second output voltage to the subsystem circuit when the first output voltage at the output end is smaller than a threshold.

Abstract: A circuit and a method generate a power-on reset signal having a leading part and a trailing part. The circuit includes a startup circuit generating the leading part of the power-on reset signal and a second circuit generating the trailing part of the power-on reset signal. The power-on reset circuit is implemented by a process which does not rely on native devices having zero threshold voltage to control a circuit generating the trailing part of the power-on reset signal.

Abstract: A circuit and a method generate a power-on reset signal having a leading part and a trailing part. The circuit includes a startup circuit generating the leading part of the power-on reset signal and a second circuit generating the trailing part of the power-on reset signal. The power-on reset circuit is implemented by a process which does not rely on native devices having zero threshold voltage to control a circuit generating the trailing part of the power-on reset signal.

Abstract: A charge pump circuit comprises a first pump stage, including a first sub-pump coupled to a first pre-charge MOSFET transistor, wherein the first sub-pump is used to pump down a gate of the first pre-charge MOSFET transistor to thereby increase the pre-charge efficiency of the first pre-charge MOSFET transistor. The higher efficiency the pre-charge MOSFET is, the lower the gate level of a pass transistor is. Thus, the charge sharing efficiency becomes better, and the body effect will be eliminated. The following pump stage is the same as the first pump stage. In addition, this pre-charging is implemented by PMOSFET only; therefore, only a single well is needed and then a small layout area can be achieved. Consequently, a high efficiency negative pump can be obtained.

Abstract: In an embodiment, a charge pump circuit comprises a first pump stage, including a first sub-pump coupled to a first pre-charge MOSFET transistor, wherein the first sub-pump is used to pump down a gate of the first pre-charge MOSFET transistor to thereby increase the pre-charge efficiency of the first pre-charge MOSFET transistor. The higher efficiency the re-charge MOSFET is, the lower the gate level of pass transistor is. Thus, the charge sharing efficiency becomes better, and the body effect will be eliminated. The following pump stage is the same as the first pump stage. In addition, this embodiment is implemented by PMOSFET only; therefore, only single well is needed and then a small layout area can be achieved. Consequently, a high efficiency negative pump can be obtained.

Abstract: A circuit and a method generate a power-on reset signal having a leading part and a trailing part. The circuit includes a startup circuit generating the leading part of the power-on reset signal and a second circuit generating the trailing part of the power-on reset signal. The power-on reset circuit is implemented by a process which does not rely on native devices having zero threshold voltage to control a circuit generating the trailing part of the power-on reset signal.