Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.

Abstract: A casing includes a housing having two bent edges and an elastic piece, and a plate. The bent edges are respectively located at two first sides of the housing, and the elastic piece is located at one of two second sides of the housing. Two hook portions of the plate are respectively protruded from the plate and are respectively provided correspondingly to two opening portions of the bent edges. A second coupling portion of the plate is provided correspondingly to a first coupling portion of the elastic piece. When the hook portions respectively pass through the opening portions along a first direction, the bent edges are in contact with the plate, and enter along a second direction a space between the hook portions and the plate, the first coupling portion is in contact with the second coupling portion along a second direction and is coupled with the second coupling portion.