Patents by Inventor Kuan-Ying LAI

Kuan-Ying LAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220077300
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 10, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Publication number: 20220069102
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 3, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Patent number: 11205705
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 21, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Patent number: 10777420
    Abstract: A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Ying Lai, Chang-Mao Wang, Hsin-Yu Hsieh
  • Publication number: 20200273714
    Abstract: A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 27, 2020
    Inventors: Kuan-Ying Lai, Chang-Mao Wang, Hsin-Yu Hsieh
  • Publication number: 20200144387
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Application
    Filed: November 29, 2018
    Publication date: May 7, 2020
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Patent number: 10505007
    Abstract: A semiconductor device includes a metal gate on a substrate, in which the metal gate includes a first work function metal (WFM) layer and the first WFM layer further includes a first vertical portion, a second vertical portion, wherein the first vertical portion and the second vertical portion comprise different heights, and a first horizontal portion connecting the first vertical portion and the second vertical portion.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Wen-Yen Huang, Kuan-Ying Lai, Shui-Yen Lu
  • Patent number: 10028905
    Abstract: A substance delivery device comprises a substrate, a plurality of dissolvable supporting structures and a plurality of carriers. The substrate attaches to a tissue. The dissolvable supporting structures are disposed on the substrate. The carriers are disposed on the dissolvable supporting structures and encapsulating substances. The present invention further provides a substance delivery method. The substance delivery device and the substance delivery method of present invention is advantageous for providing sustained release effect and rising the applicability of transdermal or transmucosal delivery techniques.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: July 24, 2018
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Mei-Chin Chen, Kuan-Ying Lai, Chun-Wei Lin, Ming-Hung Ling
  • Patent number: 10026827
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.
    Type: Grant
    Filed: April 10, 2016
    Date of Patent: July 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhen Wu, Chiu-Hsien Yeh, Po-Wen Su, Kuan-Ying Lai
  • Publication number: 20170309520
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first metal gate and a second metal gate are formed on the substrate, in which the first metal gate includes a first work function metal layer, the second metal gate includes a second work function metal layer, the first metal gate and the second metal gate include different size, and the first work function metal layer and the second work function metal layer include different thickness.
    Type: Application
    Filed: May 19, 2016
    Publication date: October 26, 2017
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Kuan-Ying Lai
  • Publication number: 20170294523
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.
    Type: Application
    Filed: April 10, 2016
    Publication date: October 12, 2017
    Inventors: Zhen Wu, Chiu-Hsien Yeh, Po-Wen Su, Kuan-Ying Lai
  • Publication number: 20150018755
    Abstract: A substance delivery device comprises a substrate, a plurality of dissolvable supporting structures and a plurality of carriers. The substrate attaches to a tissue. The dissolvable supporting structures are disposed on the substrate. The carriers are disposed on the dissolvable supporting structures and encapsulating substances. The present invention further provides a substance delivery method. The substance delivery device and the substance delivery method of present invention is advantageous for providing sustained release effect and rising the applicability of transdermal or transmucosal delivery techniques.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 15, 2015
    Inventors: Mei-Chin CHEN, Kuan-Ying LAI, Chun-Wei LIN, Ming-Hung LING