Abstract: A spike electrostatic discharge (ESD) cavity structure includes an etching stop layer including, for example, polysilicon or metal material. The etching stop layer is used as the etching stop to form an opening in the dielectric layer, inside of which a number of discharging layer pairs are formed. The opening exposes the end portions of the discharge layer pairs. The opening is a cavity and can be vacuumed or filled with air.

Abstract: A method of fabricating an interconnect structure having improved electromigration resistance. Two conductive lines are formed over a substrate and isolated by a dielectric layer. A contact/via array including a plurality of row contact/vias and column contact/vias are formed within the dielectric layer and electrically connect to the two conductive lines. The load resistors are respectively inserted into the two conductive lines close to the contact/via array. The load resistors are parallel to each other and disposed to its corresponding contact/via array. The load resistors having various resistances are formed by a plurality of slots with various lengths, which are filled with dielectrics. Accordingly, the current paths from one conductive line to the other conductive line through the contact/vias and the load resistors corresponding to the two conductive lines have identical equivalent resistance.

Abstract: A structure of a conductive line. The structure of a conductive line comprises a substrate with two conductive lines formed thereon. These two conductive lines are isolated by the formation of a dielectric layer. The conductive lines are electrically connected by a contact/via array. The contact/via array further comprises contact/via columns and contact/via rows made up of contacts/vias. Each contact/via column and contact/via row are added with a load resistor, so that the equivalent resistance of each contact/via is identical.

Abstract: A flash memory device that can be erased and programmed electrically, the flash memory device includes an array of transistor memory cell units each has N-doped source and drain regions formed in the device substrate. An N-doped buried channel is formed in the device substrate located between the source and drain regions. A P-doped floating gate is further formed substantially above the buried channel, and a control gate is formed on top of the floating gate. The different doping pattern in the buried channel and the floating gate establishes an increased programming bias voltage for the flash device when operating in its programming mode so that programming speed of the device is faster than conventional. The device can also be fabricated in smaller dimensions with improved reliability.