Abstract: A controlling method for a wireless communication device is provided. The controlling method for the wireless communication device includes: attaching a first Universal Subscriber Identity Module (USIM) to a Long-Term Evolution (LTE) network; determining whether a second USIM is camped on the LTE network; detecting whether a paging collision is happened, if the second USIM is camped on the LTE network; generating a requested International Mobile Subscriber Identity (IMSI) offset for the second USIM, if the paging collision is happened, wherein the requested IMSI offset is 1 or min(T, nB)?1, T is a default paging period and nB is a number of paging occurrences within the default paging period; transmitting an attach request with the requested IMSI offset to the LTE network for the second USIM; receiving a negotiated IMSI offset from the LTE network; and attaching the second USIM to the LTE network with the negotiated IMSI offset.

Abstract: A device includes a transistor, a backside via, and a pair of sidewall spacers. The transistor includes a gate structure, a channel layer surrounded by the gate structure, and a first source/drain structure and a second source/drain structure connected to the channel layer. The backside via is under and connected to the first source/drain structure and includes a first portion, a second portion between the first portion and the first source/drain structure, and a third portion tapering from the first portion to the second portion in a cross-sectional view. The pair of sidewall spacers are on opposite sidewalls of the second portion of the backside via but not on opposite sidewalls of the first portion of the backside via.

Abstract: A protecting method for preventing solder crack failure in an electronic product is provided. Firstly, a step (a) is performed to confirm that a crack incidence rate of a metallic solder material in a printed circuit board is high. In a step (b), a protecting mechanism of controlling the electronic product to enter an idle mode and leave the idle mode is activated. Consequently, an operating temperature of the electronic product decreases at a first average drop rate.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.

Abstract: A semiconductor device includes a first substrate, an electronic component, and a lid. The first substrate includes a first substrate top side, a first substrate bottom side opposite to the first substrate top side, a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side, and a connector structure. The electronic component is coupled to the first substrate top side and coupled to the connector structure. The lid includes a wall part including a ring part coupled to the first substrate top side, a first part of an overhang part coupled to the first substrate lateral side, and a second part of the overhang part extending from the first part of the overhang part away from the first substrate lateral side.

Abstract: A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.

Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Abstract: A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.

Abstract: A semiconductor structure includes a solder resist layer disposed on a circuit substrate and partially covering contact pads of the circuit substrate, and external terminals disposed on the solder resist layer and extending through the solder resist layer to land on the contact pads. The external terminals include a first external terminal and a second external terminal which have different heights. A first interface between the first external terminal and corresponding one of the contact pads underlying the first external terminal is less than a second interface between the second external terminal and another corresponding one of the contact pads underlying the second external terminal.

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Abstract: A semiconductor device includes: a substrate; a plurality of dies attached to a first side of the substrate; a molding material on the first side of the substrate around the plurality of dies; a first redistribution structure on a second side of the substrate opposing the first side, where the first redistribution structure includes dielectric layers and conductive features in the dielectric layers, where the conductive features include conductive lines, vias, and dummy metal patterns isolated from the conductive lines and the vias; and conductive connectors attached to a first surface of the first redistribution structure facing away from the substrate.

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.

Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

Abstract: A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.

Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.