Patents by Inventor Kuan-Yu YEH

Kuan-Yu YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240385415
    Abstract: A photographing lens assembly includes five lens elements which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. Each of the five lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The first lens element has positive refractive power. The third lens element has negative refractive power, the object-side surface of the third lens element is convex in a paraxial region thereof, and the image-side surface of the third lens element is concave in a paraxial region thereof. At least one of the object-side surface and the image-side surface of at least one lens element of the photographing lens assembly is aspheric.
    Type: Application
    Filed: June 12, 2023
    Publication date: November 21, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ting YEH, Cheng-Yu TSAI
  • Publication number: 20240387180
    Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Meng-Han Chou, Kuan-Yu Yeh, Wei-Yip Loh, Hung-Hsu Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12066606
    Abstract: An image lens assembly includes four lens groups: a first lens group, a second lens group, a third lens group and a fourth lens group along an optical path. The four lens groups include nine lens elements: a first lens element with positive refractive power, a second lens element with negative refractive power, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element, an eighth lens element and a ninth lens element along the optical path. At least one lens element of the image lens assembly has at least one inflection point. At least five lens elements of the image lens assembly are made of plastic material. When focusing or zooming, the first lens group and the fourth lens group stay stationary, while the second lens group and the third lens group move along an optical axis.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: August 20, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Kuan-Ting Yeh, Wei-Yu Chen
  • Publication number: 20240264410
    Abstract: A photographing system lens assembly includes eight lens elements, the eight lens elements being, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element, a seventh lens element and an eighth lens element. Each of the eight lens elements has an object-side surface towards the object side and an image-side surface towards the image side.
    Type: Application
    Filed: February 5, 2024
    Publication date: August 8, 2024
    Inventors: Kuan-Ting YEH, Cheng-Yu TSAI
  • Publication number: 20230369055
    Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Meng-Han Chou, Kuan-Yu Yeh, Wei-Yip Loh, Hung-Hsu Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11742210
    Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Chou, Kuan-Yu Yeh, Wei-Yip Loh, Hung-Hsu Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11222818
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiang Chao, Min-Hsiu Hung, Chun-Wen Nieh, Ya-Huei Li, Yu-Hsiang Liao, Li-Wei Chu, Kan-Ju Lin, Kuan-Yu Yeh, Chi-Hung Chuang, Chih-Wei Chang, Ching-Hwanq Su, Hung-Yi Huang, Ming-Hsing Tsai
  • Publication number: 20210407808
    Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.
    Type: Application
    Filed: April 15, 2021
    Publication date: December 30, 2021
    Inventors: Meng-Han Chou, Kuan-Yu Yeh, Wei-Yip Loh, Hung-Hsu Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11011611
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a conductive region made of silicon, germanium or a combination thereof. The semiconductor device structure also includes an insulating layer over the semiconductor substrate and a fill metal material layer in the insulating layer. In addition, the semiconductor device structure includes a nitrogen-containing metal silicide or germanide layer between the conductive region and the fill metal material layers.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Min-Hsiu Hung, Yi-Hsiang Chao, Kuan-Yu Yeh, Kan-Ju Lin, Chun-Wen Nieh, Huang-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Publication number: 20200335597
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed over the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below the gate structure. The semiconductor device structure further includes two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. The first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall. The gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Inventors: Min-Hsiu HUNG, Yi-Hsiang CHAO, Kuan-Yu YEH, Kan-Ju LIN, Chun-Wen NIEH, Huang-Yi HUANG, Chih-Wei CHANG, Ching-Hwanq SU
  • Patent number: 10700177
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min-Hsiu Hung, Yi-Hsiang Chao, Kuan-Yu Yeh, Kan-Ju Lin, Chun-Wen Nieh, Huang-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Publication number: 20200020583
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiang CHAO, Min-Hsiu HUNG, Chun-Wen NIEH, Ya-Huei LI, Yu-Hsiang LIAO, Li-Wei CHU, Kan-Ju LIN, Kuan-Yu YEH, Chi-Hung CHUANG, Chih-Wei CHANG, Ching-Hwanq SU, Hung-Yi HUANG, Ming-Hsing TSAI
  • Publication number: 20190097012
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.
    Type: Application
    Filed: April 27, 2018
    Publication date: March 28, 2019
    Inventors: Min-Hsiu HUNG, Yi-Hsiang CHAO, Kuan-Yu YEH, Kan-Ju LIN, Chun-Wen NIEH, Huang-Yi HUANG, Chih-Wei CHANG, Ching-Hwanq SU
  • Publication number: 20190025247
    Abstract: The present invention is a highly sensitive and flexible carbon nanotube forest strain sensor, comprising: a first electrode, a second electrode, a same directory queue carbon nanotube forest, and a flexible support substrate. The present invention provides a method for manufacturing a carbon nanotube forest strain sensor, the same directory queue carbon nanotube forest can be directly grown on a flexible support substrate by a chemical vapor deposition method.
    Type: Application
    Filed: July 24, 2017
    Publication date: January 24, 2019
    Inventors: Shuo-Hung CHANG, Chih-Chung SU, Kuan-Yu YEH