Abstract: The present disclosure provides a 3D memory structure such as 3D Flash memory structure applying for 3D AND flash memory and a method of forming the same. An etching stop layer is formed on a substrate including active elements. A stacked layer is formed on the etching stop layer. The stacked layer includes insulation layers and sacrificed layers stacked alternatively on the etching stop layer. A patterning process is performed on the stacked layer to form a first stacked structure above the active elements, a second stacked structure surrounding the first stacked structure, and a trench pattern separating the first stacked structure and the second stacked structure and exposing the etching stop layer. The trench pattern includes asymmetric inner sidewalls and outer sidewalls. The inner sidewalls define sidewalls of the first stacked structure. The outer sidewalls define sidewalls of the second stacked structure that face the first stacked structure.

Abstract: A three-dimension memory device, a memory circuit and a production method are provided. The three-dimension memory circuit includes a peripheral circuit, a metal layer, a buffer layer, a poly silicon layer, and a via array. The peripheral circuit is disposed on a substrate. The metal layer covers on the peripheral circuit and is electrically coupled to the peripheral circuit. The buffer layer is disposed on the metal layer. The poly silicon layer receives a reference ground voltage and is disposed on the buffer layer. The via array is disposed in the buffer layer and is used to electrically connect the metal layer and the poly silicon layer.

Abstract: A vertical memory structure comprises a stack of alternating layers of insulator material and word line material with a vertical opening through the alternating layers. One of the layers of insulating material and layers of word line material have recessed inside surfaces facing the opening. First and second conductive pillars are disposed inside the vertical opening. A data storage structure is disposed on the inside surfaces of the layers of word line material, including on the recessed inside surfaces. A semiconductor channel layer is disposed on the data storage structures around a perimeter of the vertical opening, and having first and second source/drain terminals at contacts with the first and second conductive pillars.

Abstract: An embodiment of the present disclosure provides a memory device. The memory device comprises a substrate. A plurality of word line layers are disposed over the substrate. An array of vertical NOR columns is in a first area of the plurality of word line layers. Each vertical NOR column in the array of vertical NOR columns includes a first conductive pillar and a second conductive pillar. Each vertical NOR column comprises a first plurality of memory cells arranged in a NOR configuration formed at cross points of word line layers in the plurality of word line layers with the first and second conductive pillars. An array of vertical NAND columns is in a second area of the plurality of word line layers. Each vertical NAND column in the array of vertical NAND columns includes a memory pillar. Each vertical NAND column comprises a second plurality of memory cells arranged in a NAND configuration formed at cross points of word line layers in the plurality of word line layers with the memory pillar.

Abstract: Provided is a method of forming a three-dimensional (3D) memory device including: forming a discharging layer and a stack structure on a buffer layer; forming vertical channel structures in the stack structure; forming an opening in the stack structure, wherein the opening includes two first trenches extending along a X direction and two second trenches extending along a Y direction, and the two first trenches and the two second trenches are separated from each other; forming an insulating layer on a sidewall of the opening; removing the discharging layer exposed by the insulating layer to form a cavity connecting the two first trenches and the two second trenches, thereby forming a ring-shaped opening; performing a gate replacement process to replace sacrificial layers of the stack structure by conductive layers; and filling an isolating material in the ring-shaped opening to form an isolating ring structure.

Abstract: A vertical memory structure comprises a stack of alternating layers of insulator material and word line material with a vertical opening through the alternating layers. One of the layers of insulating material and layers of word line material have recessed inside surfaces facing the opening. First and second conductive pillars are disposed inside the vertical opening. A data storage structure is disposed on the inside surfaces of the layers of word line material, including on the recessed inside surfaces.

Abstract: Provided is a memory device, including a stacked structure, a pillar, a first stop layer, and a contact plug. The stacked structure includes a plurality of conductive layers. The pillar penetrates the plurality of series-connected memory cells. The plurality of series-connected memory cells are located in a layout pattern of pillar locations at cross-points between the pillar and the conductive layers. The first stop layer covers the stacked structure and a portion of a top surface of the pillar. The contact plug passes through the first stop layer, extending into the pillar, and is electrically connected to the plurality of series-connected memory cells. The contact is landed on the contact plug, and is electrically connected to a portion of the pillar through the contact plug.

Abstract: An electron-beam lithography method includes, computing and outputting a development time of a positive-tone electron-sensitive layer and a parameter recipe of an electron-beam device by using a pattern dimension simulation system, performing a low-temperature treatment to chill a developer solution, utilizing an electron-beam to irradiate an exposure region of the positive-tone electron-sensitive layer based on the parameter recipe, and utilizing the chilled developer solution to develop a development region of the positive-tone electron-sensitive layer based on the development time. The development region is present within the exposure region, and an area of the exposure region is smaller than that of the first portion. As a result, the electron-beam lithography method may control a dimension of a development pattern of the positive-tone electron-sensitive layer more accurately, and may also shrink a minimum dimension of the development pattern of the positive-tone electron-sensitive layer.

Abstract: An electron-beam lithography method includes, computing and outputting a development time of a positive-tone electron-sensitive layer and a parameter recipe of an electron-beam device by using a pattern dimension simulation system, performing a low-temperature treatment to chill a developer solution, utilizing an electron-beam to irradiate an exposure region of the positive-tone electron-sensitive layer based on the parameter recipe, and utilizing the chilled developer solution to develop a development region of the positive-tone electron-sensitive layer based on the development time. The development region is present within the exposure region, and an area of the exposure region is smaller than that of the first portion. As a result, the electron-beam lithography method may control a dimension of a development pattern of the positive-tone electron-sensitive layer more accurately, and may also shrink a minimum dimension of the development pattern of the positive-tone electron-sensitive layer.