Patents by Inventor Kuan Zhou
Kuan Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240273057Abstract: A host system for executing an application on first and/or second reconfigurable processors is presented. The host system is operatively coupled to the first and second reconfigurable processors, whereby the first reconfigurable processors have a first architecture, and the second reconfigurable processors have a second architecture that is different than the first architecture. The host system allocates reconfigurable processors of the first and/or second reconfigurable processors for executing the application and includes an auto-discovery module that is configured to determine whether the allocated reconfigurable processors include at least one of the first reconfigurable processors.Type: ApplicationFiled: April 15, 2024Publication date: August 15, 2024Applicant: SambaNova Systems, Inc.Inventors: Greg DYKEMA, Maran WILSON, Guoyao FENG, Kuan ZHOU, Tianyu SUN, Taylor LEE, Kin Hing LEUNG, Arnav GOEL, Conrad Alexander TURLIK, Milad SHARIF
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Patent number: 12057840Abstract: A single-ended to a differential signal converter (converter) includes, in part, first, second, and third inverting elements, each having a first size, and coupled in series to form a chain of inverting elements. The converter further includes a fourth inverting element of a second size and coupled to the input of the first inverting element, a fifth inverting element of a third size and coupled to an output terminal of the first inverting element, a sixth inverting element of the third size and coupled to an output of the second inverting element, and a seventh inverting element of the second size and coupled to the output of the third inverting element. The outputs of the fourth and sixth inverting elements form a first one of the differential signals. The outputs of the fifth and seventh inverting elements form a second one of the differential signals.Type: GrantFiled: January 10, 2023Date of Patent: August 6, 2024Assignee: Synopsys, Inc.Inventors: Yue Yu, Kuan Zhou
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Patent number: 12051481Abstract: A method includes: receiving a data signal (DQ) and a clock signal (DQS); generating an indicator signal by: delaying the data signal (DQ) to generate a delayed data signal (DQ?); sampling the data signal (DQ) and the delayed data signal (DQ?) using an edge of the clock signal (DQS) to generate a first sampled value and a second sampled value; and generating the indicator signal based on the first sampled value and the second sampled value; and adjusting one or more of a DQ adjustable delay line associated with the data signal (DQ) and a DQS adjustable delay line associated with the clock signal (DQS) based on the indicator signal to synchronize the data signal (DQ) and the clock signal (DQS).Type: GrantFiled: December 7, 2022Date of Patent: July 30, 2024Assignee: SYNOPSYS, INC.Inventors: David Lin, Kuan Zhou
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Patent number: 11983141Abstract: A system for executing an application on a pool of reconfigurable processors with first and second reconfigurable processors having first and second architectures that are different from each other is presented. The system comprises an archive of configuration files with first and second configuration files for executing the application on the first and second reconfigurable processors, respectively, and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises a runtime processor that allocates reconfigurable processors for executing the application and an auto-discovery module that is configured to perform discovery of whether the reconfigurable processors include at least one of the first reconfigurable processors and whether the reconfigurable processors include at least one of the second reconfigurable processors.Type: GrantFiled: September 9, 2022Date of Patent: May 14, 2024Assignee: SambaNova Systems, Inc.Inventors: Greg Dykema, Maran Wilson, Guoyao Feng, Kuan Zhou, Tianyu Sun, Taylor Lee, Kin Hing Leung, Arnav Goel, Conrad Turlik, Milad Sharif
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Publication number: 20230259823Abstract: In a method an orchestrator of a computing system determines that results of Machine Learning model computations are available and dispatches a worker to perform model computations that include computing gradients of the results. The orchestrator determines that a set of gradients of the results is available and dispatches a gradient worker to compute a sum of the gradients. The orchestrator determines that a second set of gradients of the results is available and dispatches a second gradient worker to compute a sum of the second set of gradients. The orchestrator determines that the sums of the first and second gradients are available and dispatches a third gradient worker to compute synchronized gradients. The gradient workers compute the sums and synchronized gradients concurrent with training workers computing additional model computations results and/or gradients. A computer program product can include the method and a computing system can include the orchestrator.Type: ApplicationFiled: February 13, 2023Publication date: August 17, 2023Applicant: SambaNova Systems, Inc.Inventors: Greg DYKEMA, Fansheng CHENG, Kuan ZHOU, Arnav GOEL, Subhra MAZUMDAR, Milad SHARIF, Po-Yu WU, Bowen YANG, Qi ZHENG
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Patent number: 11722128Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: GrantFiled: June 24, 2021Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Publication number: 20230237013Abstract: A system for a data-parallel execution of at least two implementations of an application on reconfigurable processors with different layouts is presented. The system comprises a pool of reconfigurable data flow resources with data transfer resources that interconnect first and second reconfigurable processors having first and second layouts that impose respective first and second constraints for the data-parallel execution of the application. The system further comprises an archive of configuration files and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises first and second compilers that generate for the application, based on the respective first and second constraints, first and second configuration files that are stored in the archive of configuration files and adapted to be executed data-parallel compatible on respective first and second reconfigurable processors.Type: ApplicationFiled: September 9, 2022Publication date: July 27, 2023Applicant: SambaNova Systems, Inc.Inventors: Greg Dykema, Maran Wilson, Guoyao Feng, Kuan Zhou, Tianyu Sun, Taylor Lee, Kin Hing LEUNG, Arnav Goel, Conrad Turlik, Milad Sharif
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Publication number: 20230237012Abstract: A system for executing an application on a pool of reconfigurable processors with first and second reconfigurable processors having first and second architectures that are different from each other is presented. The system comprises an archive of configuration files with first and second configuration files for executing the application on the first and second reconfigurable processors, respectively, and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises a runtime processor that allocates reconfigurable processors for executing the application and an auto-discovery module that is configured to perform discovery of whether the reconfigurable processors include at least one of the first reconfigurable processors and whether the reconfigurable processors include at least one of the second reconfigurable processors.Type: ApplicationFiled: September 9, 2022Publication date: July 27, 2023Applicant: SambaNova Systems, Inc.Inventors: Greg Dykema, Maran Wilson, Guoyao Feng, Kuan Zhou, Tianyu Sun, Taylor Lee, Kin Hing LEUNG, Arnav Goel, Conrad Turlik, Milad Sharif
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Patent number: 11683470Abstract: A head-mounted display device includes a see-though display providing both eyes of a user with a view of a physical object, a processor, and a non-volatile storage device holding instructions executable by the processor to: display an image that corresponds to the physical object to a first eye of the user at an offset to the physical object; display blocking light to a second eye of the user; in response to alignment user input, move a position of the image relative to the physical object; in response to completion user input, determine the inter-pupillary distance of the user; and calibrate the head-mounted display device based on the inter-pupillary distance.Type: GrantFiled: January 11, 2022Date of Patent: June 20, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Todd Michael Lyon, Maria M. Cameron, Felicia Stephanie Williams, Scott Petill, Qi Kuan Zhou
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Patent number: 11569806Abstract: Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.Type: GrantFiled: February 2, 2022Date of Patent: January 31, 2023Assignee: Synopsys, Inc.Inventors: Kuan Zhou, David Da-Wei Lin, Vladimir Zlatkovic, Shefali Walia, Youssef Mamdouh El-Toukhy, Abdelrahman Alaa Gouda, Alexander A. Alexeyev
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Publication number: 20220247398Abstract: Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry.Type: ApplicationFiled: February 2, 2022Publication date: August 4, 2022Inventors: Kuan ZHOU, David Da-Wei LIN, Vladimir ZLATKOVIC, Shefali WALIA, Youssef Mamdouh EL-TOUKHY, Abdelrahman Alaa GOUDA, Alexander A. ALEXEYEV
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Publication number: 20220132099Abstract: A head-mounted display device includes a see-though display providing both eyes of a user with a view of a physical object, a processor, and a non-volatile storage device holding instructions executable by the processor to: display an image that corresponds to the physical object to a first eye of the user at an offset to the physical object; display blocking light to a second eye of the user; in response to alignment user input, move a position of the image relative to the physical object; in response to completion user input, determine the inter-pupillary distance of the user; and calibrate the head-mounted display device based on the inter-pupillary distance.Type: ApplicationFiled: January 11, 2022Publication date: April 28, 2022Applicant: Microsoft Technology Licensing, LLCInventors: Todd Michael Lyon, Maria M. Cameron, Felicia Stephanie Williams, Scott Petill, Qi Kuan Zhou
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Patent number: 11252399Abstract: A head-mounted display device is disclosed that includes an at least partially see-though display, a processor, and a non-volatile storage device holding instructions executable by the processor to: select an image that corresponds to a physical object viewable by the user; display the image at a perceived offset to the physical object; in response to alignment user input, move a perceived position of the image relative to the physical object; output an instruction to provide completion user input when the image appears to align with the physical object; when the completion user input is received, determine the inter-pupillary distance of the user; and calibrate the head mounted display device based on the inter-pupillary distance.Type: GrantFiled: May 28, 2015Date of Patent: February 15, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Todd Michael Lyon, Maria M. Cameron, Felicia Stephanie Williams, Scott Petill, Qi Kuan Zhou
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Publication number: 20210320652Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Applicant: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Patent number: 11070200Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: GrantFiled: September 27, 2018Date of Patent: July 20, 2021Assignee: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Publication number: 20200106430Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.Type: ApplicationFiled: September 27, 2018Publication date: April 2, 2020Applicant: Intel CorporationInventors: Aaron Martin, Roger Cheng, Hari Venkatramani, Navneet Dour, Mozhgan Mansuri, Bryan Casper, Frank O'Mahony, Ganesh Balamurugan, Ajay Balankutty, Kuan Zhou, Sridhar Tirumalai, Krishnamurthy Venkataramana, Alex Thomas, Quoc Nguyen
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Publication number: 20180190331Abstract: An embodiment of a receiver apparatus may include high pass components to pass high frequency components of an input signal, low pass components to pass low frequency components of the input signal, and an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components, wherein the low pass components include a level shifter to shift a common mode voltage level of the input signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventors: Kuan Zhou, Bruce Querbach, Li Pan
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Patent number: 10014036Abstract: An embodiment of a receiver apparatus may include high pass components to pass high frequency components of an input signal, low pass components to pass low frequency components of the input signal, and an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components, wherein the low pass components include a level shifter to shift a common mode voltage level of the input signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices. Other embodiments are disclosed and claimed.Type: GrantFiled: December 29, 2016Date of Patent: July 3, 2018Assignee: Intel CorporationInventors: Kuan Zhou, Bruce Querbach, Li Pan
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Patent number: 9746675Abstract: A head-mounted display device is disclosed, which includes an at least partially see-through display, a processor configured to detect a physical feature, generate an alignment hologram based on the physical feature, determine a view of the alignment hologram based on a default view matrix for a first eye of a user of the head-mounted display device, display the view of the alignment hologram to the first eye of the user on the at least partially see-through display, output an instruction to the user to enter an adjustment input to visually align the alignment hologram with the physical feature, determine a calibrated view matrix based on the default view matrix and the adjustment input, and adjust a view matrix setting of the head-mounted display device based on the calibrated view matrix.Type: GrantFiled: May 28, 2015Date of Patent: August 29, 2017Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Quentin Simon Charles Miller, Drew Steedly, Denis Demandolx, Youding Zhu, Qi Kuan Zhou, Todd Michael Lyon
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Patent number: 9658686Abstract: Various embodiments relating to using motion based view matrix tuning to calibrate a head-mounted display device are disclosed. In one embodiment, the holograms are rendered with different view matrices, each view matrix corresponding to a different inter-pupillary distance. Upon selection by the user of the most stable hologram, the head-mounted display device can be calibrated to the inter-pupillary distance corresponding to the selected most stable hologram.Type: GrantFiled: May 28, 2015Date of Patent: May 23, 2017Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Quentin Simon Charles Miller, Drew Steedly, Denis Demandolx, Youding Zhu, Qi Kuan Zhou, Todd Michael Lyon