Abstract: An ac-powered LED light engine coupled between a rectifier and a plurality of extrinsic LED sub-arrays is provided. The ac-powered LED light engine comprises a plurality of normally closed bypass switches, a normally closed current regulator, and a plurality of switch controllers. Each of the normally closed bypass switches is connected in parallel with a corresponding LED sub-array except for the topmost or the bottommost LED sub-array and shuttles between three switch states: ON, REGULATION, and OFF. The normally closed current regulator is coupled to the normally closed bypass switches and used to regulate the highest LED current level near the peak of an extrinsic mains voltage. Each of the switch controllers is coupled to a corresponding bypass switch as a feedback network and takes control of the three switch states according to a corresponding current sense signal.

Abstract: Disclosed are control circuits capable of auto-configuring two LED arrays either in parallel when the two LED arrays are operating off of 100±20% V AC voltage sources or in series when the two LED arrays are operating off of 200±20% V AC voltage sources according to the detection of the AC input voltage magnitude. The disclosed control circuits, ruling over the parallel or series configuration of the two LED arrays, could be implemented in discrete forms or as integrated circuits (IC).

Abstract: Disclosed are novel AC-powered LED light engines for Solid State Lighting (SSL) able to achieve a high PF and a low THD without a traditional PFC. Getting rid of bulky, and costly magnetic components, short-life electrolytic capacitor, and EMI-causing fast switching, the disclosed AC-powered LED light engines ushers in a cost-effective, and energy-efficient LED driver design while eliminating the short-life electrolytic capacitor in an LED driver and reducing the Total Cost of Ownership (TOC). Thanks to no bulky components, the disclosed AC-powered LED light engines in a discrete or an integrated circuit form could be applied to the increasingly popular Driver-on-Board (DoB) design. Aside from being TRIAC-dimmable via legacy phase-cut dimmers, the disclosed LED light engines could also be made PWM-, analog-, or rheostat-dimmable with the incorporation of an appropriate dimming circuit to modulate the average LED current, adding more flexibility and versatility to dimming applications.

Abstract: Disclosed are novel AC-powered LED light engines for Solid State Lighting (SSL) able to achieve a high PF and a low THD without a traditional PFC. Getting rid of bulky, and costly magnetic components, short-life electrolytic capacitor, and EMI-causing fast switching, the disclosed AC-powered LED light engines ushers in a cost-effective, and energy-efficient LED driver design while eliminating the short-life electrolytic capacitor in an LED driver and reducing the Total Cost of Ownership (TOC). Thanks to no bulky components, the disclosed AC-powered LED light engines in a discrete or an integrated circuit form could be applied to the increasingly popular Driver-on-Board (DoB) design. Aside from being TRIAC-dimmable via legacy phase-cut dimmers, the disclosed LED light engines could also be made PWM-, analog-, or rheostat-dimmable with the incorporation of an appropriate dimming circuit to modulate the average LED current, adding more flexibility and versatility to dimming applications.

Abstract: Disclosed are electronic control gears for LED light engines able to improve power factor by way of gearing up or down the LED current and the AC input current in response to and in synchronization with the AC input voltage. Moreover, the disclosed electronic control gears could further reduce flicker phenomenon and total harmonic distortion when used in collocation with disclosed valley fillers, filling the LED current valleys only during the dead time, and in conjunction with disclosed dummy loads, ramping up or down the AC input current only during the dead time.

Abstract: Disclosed are control circuits capable of auto-configuring two LED arrays either in parallel when the two LED arrays are operating off of 100±20% V AC voltage sources or in series when the two LED arrays are operating off of 200±20% V AC voltage sources according to the detection of the AC input voltage magnitude. The disclosed control circuits, ruling over the parallel or series configuration of the two LED arrays, could be implemented in discrete forms or as integrated circuits (IC).

Abstract: An ac-powered LED light engine coupled between a rectifier and a plurality of extrinsic LED sub-arrays is provided. The ac-powered LED light engine comprises a plurality of normally closed bypass switches, a normally closed current regulator, and a plurality of switch controllers. Each of the normally closed bypass switches is connected in parallel with a corresponding LED sub-array except for the topmost or the bottommost LED sub-array and shuttles between three switch states: ON, REGULATION, and OFF. The normally closed current regulator is coupled to the normally closed bypass switches and used to regulate the highest LED current level near the peak of an extrinsic mains voltage. Each of the switch controllers is coupled to a corresponding bypass switch as a feedback network and takes control of the three switch states according to a corresponding current sense signal.

Abstract: Disclosed are electronic control gears for LED light engines able to improve power factor by way of gearing up or down the LED current and the AC input current in response to and in synchronization with the AC input voltage. Moreover, the disclosed electronic control gears could further reduce flicker phenomenon and total harmonic distortion when used in collocation with disclosed valley fillers, filling the LED current valleys only during the dead time, and in conjunction with disclosed dummy loads, ramping up or down the AC input current only during the dead time.

Abstract: The present invention relates to a stacked semiconductor chip package comprising a substrate, a first chip, a plate, and a second chip The first chip is mounted on the substrate. The second chip comprises two opposed longitudinal sides defining a first length. The plate is mounted between the first chip and the second chip, and connects the first chip and the second chip. Corresponding to the two longitudinal sides of the second chip, the plate has two opposed longitudinal sides defining a second length. The second length is larger than the first length to expose the opposed longitudinal sides of the plate. An overflow adhesive portion is formed between the plate and the second chip, and the overflow adhesive portion exposes on the plate. Therefore, the testing instrument can detect the size of the overflow adhesive portion and the thickness of the adhesive layer so as to control the quality of the stacked semiconductor chip package.

Abstract: A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40° C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.

Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a lower chip to a substrate or a lead frame; (b) electrically coupling the lower chip to the substrate or the lead frame; (c) providing a dummy chip with a film adhesive on a upper surface thereof; (d) attaching the dummy chip to the lower chip through an adhesive layer wherein a lower surface of the dummy chip is in contact with the adhesive layer; (e) attaching an upper chip to the dummy chip through the film adhesive; (f) electrically coupling the upper chip to the substrate or the lead frame; and (g) encapsulating the lower chip and the upper chip against a portion of the substrate or the lead frame with a molding compound. Since the dummy chip is bonded to the upper chip via a film adhesive, it is not necessary to monitor the thickness of the film adhesive after the upper chip is bonded to the dummy chip.

Abstract: A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

Abstract: The present invention relates to a stacked semiconductor chip package comprising a substrate, a first chip, a plate, and a second chip The first chip is mounted on the substrate. The second chip comprises two opposed longitudinal sides defining a first length. The plate is mounted between the first chip and the second chip, and connects the first chip and the second chip. Corresponding to the two longitudinal sides of the second chip, the plate has two opposed longitudinal sides defining a second length. The second length is larger than the first length to expose the opposed longitudinal sides of the plate. An overflow adhesive portion is formed between the plate and the second chip, and the overflow adhesive portion exposes on the plate. Therefore, the testing instrument can detect the size of the overflow adhesive portion and the thickness of the adhesive layer so as to control the quality of the stacked semiconductor chip package.

Abstract: A method for fabricating a stacked chip package comprises the steps of: (a) attaching a lower chip to a substrate or a lead frame; (b) electrically coupling the lower chip to the substrate or the lead frame; (c) providing a dummy chip with a film adhesive on a upper surface thereof; (d) attaching the dummy chip to the lower chip through an adhesive layer wherein a lower surface of the dummy chip is in contact with the adhesive layer; (e) attaching an upper chip to the dummy chip through the film adhesive; (f) electrically coupling the upper chip to the substrate or the lead frame; and (g) encapsulating the lower chip and the upper chip against a portion of the substrate or the lead frame with a molding compound. Since the dummy chip is bonded to the upper chip via a film adhesive, it is not necessary to monitor the thickness of the film adhesive after the upper chip is bonded to the dummy chip.

Abstract: A multichip module has at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. In some embodiments, the semiconductor chips may have a plurality of bonding pads along only two mutually perpendicular side edges thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bonding pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

Abstract: A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

Abstract: A multichip module comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. Therefore, all semiconductor chips can be wire bonded simultaneously after stacking the chips on the substrate. This allows wire bonding of all chips to be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.

Abstract: A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40° C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.