Abstract: An integrated circuit (IC) structure includes a fin structure protruding from a semiconductor substrate, the fin structure including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction. The IC structure also includes a first standard cell including a first metal gate stack engaged with the first portion, a second standard cell including a second metal gate stack engaged with the second portion, and a filler cell disposed between the first standard cell and the second standard cell, where the filler cell includes the third portion that connects the first portion to the second portion.

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.

Abstract: An IC structure includes first, second, third and fourth transistors on a substrate, and first and second metallization layers over the transistors. The first metallization layer has a plurality of first metal lines extending laterally along a first direction and having a first line width measured in a second direction. One or more of the first metal lines are part of a first net electrically connecting the first and second transistors. The second metallization layer has a plurality of second metal lines extending laterally along the second direction and having a second line width measured in the first direction and less than the first line width. One or more of the second metal lines are part of a second net electrically connecting the third and fourth transistors, and a total length of the second net is less than a total length of the first net.

Abstract: A gateway apparatus, a detecting method of malicious domain and hacked host thereof, and a non-transitory computer readable medium are provided. The detecting method includes the following steps: capturing network traffics, and parsing traces and channels from the network traffics. Each channel is related to a link between a domain and an Internet Protocol (IP) address, and each trace is related to an http request requested from the IP address for asking the domain. Then, a trace-channel behavior graph is established. The malicious degree model is trained based on the trace-channel behavior graph and threat intelligence. Accordingly, a malicious degree of an unknown channel can be determined, thereby providing a detecting method with high precision.

Abstract: A gateway apparatus, a detecting method of malicious domain and hacked host thereof, and a non-transitory computer readable medium are provided. The detecting method includes the following steps: capturing network traffics, and parsing traces and channels from the network traffics. Each channel is related to a link between a domain and an Internet Protocol (IP) address, and each trace is related to an http request requested from the IP address for asking the domain. Then, a trace-channel behavior graph is established. The malicious degree model is trained based on the trace-channel behavior graph and threat intelligence. Accordingly, a malicious degree of an unknown channel can be determined, thereby providing a detecting method with high precision.

Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.

Abstract: An integrated circuit includes: a first spine formed on a first conductive layer of the integrated circuit, the spine runs in a first direction; a first plurality of ribs formed on a second conductive layer of the integrated circuit, the first plurality of ribs run parallel to one another in a second direction that is orthogonal to the first direction and overlap respective portions of the first spine; a first plurality of interlayer vias formed between the first and second conductive layers, each of the plurality of interlayer vias electrically couple respective ones of the first plurality of ribs to the first spine at the respective portions of overlap; and a plurality of signal lines formed on the second conductive layer and running parallel to one another in the second direction.

Abstract: An integrated circuit includes: a first spine formed on a first conductive layer of the integrated circuit, the spine runs in a first direction; a first plurality of ribs formed on a second conductive layer of the integrated circuit, the first plurality of ribs run parallel to one another in a second direction that is orthogonal to the first direction and overlap respective portions of the first spine; a first plurality of interlayer vias formed between the first and second conductive layers, each of the plurality of interlayer vias electrically couple respective ones of the first plurality of ribs to the first spine at the respective portions of overlap; and a plurality of signal lines formed on the second conductive layer and running parallel to one another in the second direction.

Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.