Abstract: The skew between a received clock signal and a received data signal that are source synchronous, is accounted for such that stable bit values of the received data signal may be sampled. For programmable skew cancellation, a skew value corresponding to the amount of the skew is determined and programmed into a data storage device. Sampling clock signals of the same frequency but different phases are generated from the clock signal, and one of the sampling clock signals having the desired phase is selected depending on the programmed skew value. Alternatively, for automatic skew cancellation, a phase locked loop compares the received data signal to one of the sampling clock signals to determine the skew value for selecting the sampling clock signal having the desired phase. Stable bit values of the data signal are then sampled with the selected sampling clock signal.

Abstract: A common mode logic (CML) circuit having an improved bias circuit and an active MOS load operating exclusively in the triode region to provide improved performance characteristics including a high speed of operation. The bias circuit of the CML circuit comprises a pair of MOS transistors, one of which has an aspect ratio (W.sub.P /L.sub.P) and the other of which has an aspect ratio (W.sub.P /L.sub.P)/n, wherein 1<n<4. This configuration causes a third MOS transistor in the bias circuit to operate exclusively in the triode region. The CML circuit also includes a logic portion, which may be a logic gate or flip-flop, having a plurality of pairs of input MOS transistors for receiving differential input signals. In accordance with the invention, the logic portion has load MOS transistors which operate exclusively in the triode region.

Abstract: A low power RAM device including a bit line precharge circuit which selectively precharges only those bit lines which will be read in an effort to minimize precharge and overall RAM power consumption. The preferred RAM precharge circuit uses a precharge device in the sense amplifier as the primary bit line precharge device to selectively connect and precharge the selected bit line through a column MUX. The preferred RAM precharge also includes secondary bit line precharge devices for each bit line to enable trickle charging thereof to prevent hazardous RAM data corruption. Since RAM corruption occurs only after several clock cycles, the secondary precharge devices comprise small transistors having only 1/20 the size of normal precharge device to conserve precharge power requirements.