Patents by Inventor Kuang Kao
Kuang Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978764Abstract: A capacitor structure includes a first electrode, a second electrode, a third electrode, a first dielectric layer and a second dielectric layer. The second electrode is disposed over the first electrode. The third electrode is disposed over the second electrode. The first dielectric layer is disposed between the first electrode and the second electrode. The second dielectric layer is disposed between the second electrode and the third electrode. The third electrode contacts the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.Type: GrantFiled: June 10, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chih-Kuang Kao
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Publication number: 20240038486Abstract: An apparatus for observing a sample using a charged particle beam includes an ion beam column configured to generate and direct an ion beam, an electron beam column configured to generate and direct an electron beam, a vacuum chamber for housing the sample, and a probe positioned in the vacuum chamber. The probe is configured to provide electrical connection between the sample and a power supply.Type: ApplicationFiled: April 10, 2023Publication date: February 1, 2024Inventors: Yu-Ching Chiu, Chih-Kuang Kao, Huei-Wen Yang
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Publication number: 20240038605Abstract: A testline structure of a semiconductor device includes a substrate layer, a frontside insulating layer atop the substrate layer, a backside insulating layer under the substrate layer, and a probe pad structure vertically extending through the frontside insulating layer, the substrate layer, and the backside insulating layer. The probe pad structure includes a frontside probe pad in the frontside insulating layer and a backside probe pad in the backside insulating layer.Type: ApplicationFiled: April 28, 2023Publication date: February 1, 2024Inventors: Yu-Ching Chiu, Chih-Kuang Kao, Huei-Wen Yang
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Publication number: 20230333158Abstract: The present disclosure describes a method that includes scanning a circuit layout and identifying layout regions of the circuit layout. The method further includes placing unit cells in a layout region of the layout regions and forming a micro pad structure at a border of a unit cell of the unit cells. The micro pad structure includes interconnect structures that are electrically connected to the unit cell.Type: ApplicationFiled: April 13, 2022Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Ching Chiu, Chih-Feng Ku, Chih-Kuang Kao
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Publication number: 20230207450Abstract: The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.Type: ApplicationFiled: February 17, 2023Publication date: June 29, 2023Inventors: CHIH-KUANG KAO, TA-CHIH PENG, MING-HONG KAO, HUEI-WEN YANG
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Patent number: 11587863Abstract: The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.Type: GrantFiled: December 9, 2020Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chih-Kuang Kao, Ta-Chih Peng, Ming-Hong Kao, Huei-Wen Yang
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Publication number: 20220302247Abstract: A capacitor structure includes a first electrode, a second electrode, a third electrode, a first dielectric layer and a second dielectric layer. The second electrode is disposed over the first electrode. The third electrode is disposed over the second electrode. The first dielectric layer is disposed between the first electrode and the second electrode. The second dielectric layer is disposed between the second electrode and the third electrode. The third electrode contacts the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.Type: ApplicationFiled: June 10, 2022Publication date: September 22, 2022Inventor: CHIH-KUANG KAO
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Patent number: 11362169Abstract: A capacitor structure includes an insulative layer, a first electrode over the insulative layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The first electrode includes a first portion extending along a lateral direction of the insulative layer and a second portion connected to the first portion and extending along a depth direction of the insulative layer. The dielectric layer is substantially conformal with respect to a profile of the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.Type: GrantFiled: August 31, 2020Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chih-Kuang Kao
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Publication number: 20210118795Abstract: The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor: and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.Type: ApplicationFiled: December 9, 2020Publication date: April 22, 2021Inventors: CHIH-KUANG KAO, TA-CHIH PENG, MING-HONG KAO, HUEI-WEN YANG
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Publication number: 20200403063Abstract: A capacitor structure includes an insulative layer, a first electrode over the insulative layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The first electrode includes a first portion extending along a lateral direction of the insulative layer and a second portion connected to the first portion and extending along a depth direction of the insulative layer. The dielectric layer is substantially conformal with respect to a profile of the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.Type: ApplicationFiled: August 31, 2020Publication date: December 24, 2020Inventor: CHIH-KUANG KAO
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Patent number: 10867903Abstract: The present disclosure provides a semiconductor package, including at least two conductors and a first dielectric partially surrounding the at least two conductors, a capacitor substantially under the first dielectric, and a second dielectric over and lining along the first dielectric and top portions of the at least two conductors. The at least two conductors are respectively configured as an input/output (I/O) terminal of the semiconductor package. The capacitor includes a first electrode extending along a first direction and electrically connected with one of the at least two conductors, and a second electrode extending along a second direction opposite to the first direction and electrically connected to the other one of the at least two conductors. The second dielectric provides a compressive stress to the first dielectric. A method of forming the semiconductor package is also provided.Type: GrantFiled: November 9, 2018Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chih-Kuang Kao, Ta-Chih Peng, Ming-Hong Kao, Huei-Wen Yang
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Patent number: 10763325Abstract: A capacitor structure includes an insulative layer, a first electrode over the insulative layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The first electrode includes a first portion extending along a lateral direction of the insulative layer and a second portion connected to the first portion and extending along a depth direction of the insulative layer. The dielectric layer is substantially conformal with respect to a profile of the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.Type: GrantFiled: August 28, 2018Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chih-Kuang Kao
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Publication number: 20200075710Abstract: A capacitor structure includes an insulative layer, a first electrode over the insulative layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The first electrode includes a first portion extending along a lateral direction of the insulative layer and a second portion connected to the first portion and extending along a depth direction of the insulative layer. The dielectric layer is substantially conformal with respect to a profile of the first electrode. A semiconductor structure thereof and a method for forming the same are also provided.Type: ApplicationFiled: August 28, 2018Publication date: March 5, 2020Inventor: CHIH-KUANG KAO
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Publication number: 20200035596Abstract: The present disclosure provides a semiconductor package, including at least two conductors and a first dielectric partially surrounding the at least two conductors, a capacitor substantially under the first dielectric, and a second dielectric over and lining along the first dielectric and top portions of the at least two conductors. The at least two conductors are respectively configured as an input/output (I/O) terminal of the semiconductor package. The capacitor includes a first electrode extending along a first direction and electrically connected with one of the at least two conductors, and a second electrode extending along a second direction opposite to the first direction and electrically connected to the other one of the at least two conductors. The second dielectric provides a compressive stress to the first dielectric. A method of forming the semiconductor package is also provided.Type: ApplicationFiled: November 9, 2018Publication date: January 30, 2020Inventors: CHIH-KUANG KAO, TA-CHIH PENG, MING-HONG KAO, HUEI-WEN YANG
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Publication number: 20190209083Abstract: A monitoring system for infant includes image sensors, a face region determination module, a human face identification module, a non-contact physiological information measurement module and a physiological information determination module. The image sensors are configured to capture images consecutively. The face region determination module is configured to determine whether images include a face region. When not include, the face region determination module outputs a first warning information and when include, the human face identification module is configured to identify a monitored person in images to extract the historical information. The non-contact physiological information measurement module is configured to calculate color difference of each pixel of the face region, output heartbeat waveform and calculate physiological information.Type: ApplicationFiled: January 8, 2019Publication date: July 11, 2019Inventors: Bing-Fei Wu, Kuan-Hung Chen, Meng-Liang Chung, Po-Wei Huang, Tsong-Yang Tsou, Yun-Wei Chu, Han-Kuang Kao
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Patent number: 9112004Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.Type: GrantFiled: December 18, 2013Date of Patent: August 18, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Kuang Kao, Huei-Wen Yang, Yung-Sheng Huang, Yu-Wen Lin
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Publication number: 20140106562Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Kuang Kao, Huei-Wen Yang, Yung-Sheng Huang, Yu-Wen Lin
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Patent number: 8653663Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.Type: GrantFiled: April 9, 2010Date of Patent: February 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Kuang Kao, Huei-Wen Yang, Yung-Sheng Huang, Yu-Wen Lin
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Publication number: 20110101529Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.Type: ApplicationFiled: April 9, 2010Publication date: May 5, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Kuang KAO, Huei-Wen YANG, Yung-Sheng HUANG, Yu-Wen LIN
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Publication number: 20050003120Abstract: A method of fabricating glow-in-the-dark gazing globes or other objects, as well as the articles that result. The method comprises the steps of providing a hollow form having an inner wall made from a transparent or translucent material, the form including an aperture for gaining access to the interior thereof, and introducing one more photoluminescence or phosphorescent pigments into the form through the aperture so that they cling to the inner wall. In alternative embodiments, the pigments may be applied without an adhesive, as by naturally cling, vacuum evaporation, or other techniques. In a gazing globe embodiment, a stand may be included. In the preferred embodiment the method further includes the step of applying an adhesive to the inner wall of the form prior to the step of introducing one more photoluminescence of phosphorescent pigments. A plurality of different pigments may be introduced into the form to create a decorative or swirling effect.Type: ApplicationFiled: April 27, 2004Publication date: January 6, 2005Inventor: Kuang Kao