Patents by Inventor Kuang-Neng Chung

Kuang-Neng Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9526171
    Abstract: A package structure is provided, which includes: a substrate having opposite first and second surfaces; at least an electronic element disposed on the first surface of the substrate; and an encapsulant formed on the first surface of the substrate for encapsulating the electronic element. The encapsulant has a non-rectangular shape so as to reduce an ineffective space in the encapsulant.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: December 20, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Liang Shih, Hsin-Lung Chung, Te-Fang Chu, Hao-Ju Fang, Kuang-Neng Chung
  • Patent number: 9257394
    Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a substrate having at least a carrying region and a cutting region defined on a surface thereof, wherein the cutting region surrounds the carrying region; disposing at least an electronic element on the carrying region of the substrate; disposing a shield having a recess portion and at least a positioning member extending outwards, on the carrying region of the substrate with the electronic element received in the recess portion and the positioning member extending outwards to the cutting region; and performing a cutting process along the cutting region to remove portions of the positioning member and the substrate. Therefore, the shield is precisely positioned on the substrate.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: February 9, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Kuang-Neng Chung, Hsin-Lung Chung, Tien-Chung Huang, Tsung-Hsien Hsu
  • Publication number: 20150366085
    Abstract: A package structure is provided, which includes: a substrate having opposite first and second surfaces; at least an electronic element disposed on the first surface of the substrate; and an encapsulant formed on the first surface of the substrate for encapsulating the electronic element. The encapsulant has a non-rectangular shape so as to reduce an ineffective space in the encapsulant.
    Type: Application
    Filed: December 9, 2014
    Publication date: December 17, 2015
    Inventors: Chi-Liang Shih, Hsin-Lung Chung, Te-Fang Chu, Hao-Ju Fang, Kuang-Neng Chung
  • Publication number: 20140312473
    Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a substrate having at least a carrying region and a cutting region defined on a surface thereof, wherein the cutting region surrounds the carrying region; disposing at least an electronic element on the carrying region of the substrate; disposing a shield having a recess portion and at least a positioning member extending outwards, on the carrying region of the substrate with the electronic element received in the recess portion and the positioning member extending outwards to the cutting region; and performing a cutting process along the cutting region to remove portions of the positioning member and the substrate. Therefore, the shield is precisely positioned on the substrate.
    Type: Application
    Filed: June 17, 2013
    Publication date: October 23, 2014
    Inventors: Kuang-Neng Chung, Hsin-Lung Chung, Tien-Chung Huang, Tsung-Hsien Hsu
  • Publication number: 20120170162
    Abstract: A semiconductor package is provided, which includes a substrate unit having conductive pads and ESD protection pads formed on a bottom surface thereof; an encapsulant covering a top surface of the substrate unit; and a metal layer disposed on a top surface of the encapsulant and having connecting extensions formed on side surfaces of the substrate unit and the encapsulant for electrically connecting the ESD protection pads, wherein portions of the side surfaces of the substrate unit corresponding in position to the conductive pads are exposed from the metal layer so as to ensure that solder bumps subsequently formed to connect the conductive pads of the semiconductor package to a circuit board are not in contact with the metal layer, thereby effectively avoiding the risk of short circuits.
    Type: Application
    Filed: March 22, 2011
    Publication date: July 5, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hao-Ju Fang, Hsin-Lung Chung, Kuang-Neng Chung, Chien-Cheng Lin, Heng-Cheng Chu