Abstract: A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.

Abstract: A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.

Abstract: A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.

Abstract: A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A non-volatile memory includes a substrate, a plurality of data storage elements positioned on the substrate, a plurality of control gates positioned above the data storage elements, an insulating layer positioned on surfaces and sidewalls of the control gates, and a bit-line positioned on the insulating layer to cross the control gates.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

Abstract: A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.

Abstract: A non-volatile memory includes a substrate, a plurality of data storage elements positioned on the substrate, a plurality of control gates positioned above the data storage elements, an insulating layer positioned on surfaces and sidewalls of the control gates, and a bit-line positioned on the insulating layer to cross the control gates.

Abstract: A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.