Patents by Inventor Kuang-Po Hsueh

Kuang-Po Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145478
    Abstract: A GaN HEMT with a stacked multilayer 3D structure is proposed, which is formed by re-growing a GaN layer, fabricated a second HEMT on a dielectric protective layer and connected the source, gate or drain electrodes of the respective GaN HEMT. Process is repeated to form at least three layers GaN HEMT structure, one stacked on top of the other, with each electrode of individual GaN HEMT connected by a deep etching process. Bonding pads of the HEMT device are formed on the uppermost layer of the device. The multilayer 3D GaN HEMT device will be manufactured based on stacking one layer of GaN HEMT following one layer of protection layer. In this way, the layout area of the GaN HEMT device can be reduced and the current density per unit area can be increased, thereby reducing the overall packaged volume.
    Type: Application
    Filed: November 24, 2022
    Publication date: May 2, 2024
    Inventor: Kuang-Po Hsueh
  • Publication number: 20230268431
    Abstract: A process integration method for connecting the electrode of the normally-off or normally-on GaN-based HEMT to the backside electrode by a deep etching process. Among the three electrodes of each HEMT, a single electrode or multiple electrodes can be connected to the backside electrode. The electrodes to be connected to the backside electrode through an additional deep etching process. Therefore, there is no need to place PADs on various positions as wire bonding electrodes on the upper layer of device, which can reduce the area of the device layout and use the back metal to connect the package frame base island to reduce the wire bonding parasitic effect. A new structure proposed is a design of connecting the electrode and the backside electrode of the normally-off or normally-on GaN-based HEMTs. This process integration technology not only reduce the layout area, but also reduce the parasitic effect of the packaging.
    Type: Application
    Filed: April 13, 2022
    Publication date: August 24, 2023
    Inventor: Kuang-Po Hsueh
  • Patent number: 7759172
    Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: July 20, 2010
    Assignee: National Central University
    Inventors: Yue-Ming Hsin, Jinn-Kong Sheu, Kuang-Po Hsueh
  • Patent number: 7622788
    Abstract: A gallium nitride heterojunction bipolar transistor with a p-type strained InGaN base layer is provided. The gallium nitride heterojunction bipolar transistor includes a substrate, a highly doped collector contact layer located over the substrate, a low doped collector layer located over the collector contact layer, a p-type base layer located over the collector layer, a highly doped strained InGaN base layer located over the p-type base layer, a emitter layer located over the p-type strained InGaN base layer, a highly doped emitter contact layer located over the emitter layer, and an emitter metal electrode, a base metal electrode, and a collector metal electrode respectively located on the emitter contact layer, the p-type strained InGaN base layer, and the collector contact layer.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: November 24, 2009
    Assignee: National Central University
    Inventors: Yue-Ming Hsin, Jinn-Kong Sheu, Kuang-Po Hsueh
  • Publication number: 20080299714
    Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.
    Type: Application
    Filed: August 12, 2008
    Publication date: December 4, 2008
    Applicant: NATIONAL CENTRAL UNIVERSITY
    Inventors: Yue-Ming Hsin, Jinn-Kong Sheu, Kuang-Po Hsueh
  • Publication number: 20080197422
    Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.
    Type: Application
    Filed: February 20, 2007
    Publication date: August 21, 2008
    Applicant: National Central University
    Inventors: Yue-Ming Hsin, Jinn-Kong Sheu, Kuang-Po Hsueh
  • Publication number: 20070114518
    Abstract: A gallium nitride heterojunction bipolar transistor with a p-type strained InGaN base layer is provided. The gallium nitride heterojunction bipolar transistor includes a substrate, a highly doped collector contact layer located over the substrate, a low doped collector layer located over the collector contact layer, a p-type base layer located over the collector layer, a highly doped strained InGaN base layer located over the p-type base layer, a emitter layer located over the p-type strained InGaN base layer, a highly doped emitter contact layer located over the emitter layer, and an emitter metal electrode, a base metal electrode, and a collector metal electrode respectively located on the emitter contact layer, the p-type strained InGaN base layer, and the collector contact layer.
    Type: Application
    Filed: May 30, 2006
    Publication date: May 24, 2007
    Inventors: Yue-Ming Hsin, Jinn-Kong Sheu, Kuang-Po Hsueh