Patents by Inventor Kuang-Wei Cheng

Kuang-Wei Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10153338
    Abstract: A method of forming a device includes forming a through via extending into a substrate. The method further includes forming a first insulating layer over the surface of the substrate. The method further includes forming a first metallization layer in the first insulating layer and electrically connected to the through via. The method further includes forming a capacitor over the first metallization layer, wherein the capacitor comprises a first capacitor dielectric layer and a second capacitor dielectric layer. The method further includes depositing a continuous second insulating layer over the first insulating layer. The capacitor is within the second insulating layer. The method further includes depositing a third insulating layer over the second insulating layer. The method further includes forming a second metallization layer in the third insulating layer. A bottom surface of the second metallization layer is below a bottom surface of the third insulating layer.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hua Chang, Der-Chyang Yeh, Kuang-Wei Cheng, Yuan-Hung Liu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
  • Publication number: 20170229534
    Abstract: A method of forming a device includes forming a through via extending into a substrate. The method further includes forming a first insulating layer over the surface of the substrate. The method further includes forming a first metallization layer in the first insulating layer and electrically connected to the through via. The method further includes forming a capacitor over the first metallization layer, wherein the capacitor comprises a first capacitor dielectric layer and a second capacitor dielectric layer. The method further includes depositing a continuous second insulating layer over the first insulating layer. The capacitor is within the second insulating layer. The method further includes depositing a third insulating layer over the second insulating layer. The method further includes forming a second metallization layer in the third insulating layer. A bottom surface of the second metallization layer is below a bottom surface of the third insulating layer.
    Type: Application
    Filed: April 26, 2017
    Publication date: August 10, 2017
    Inventors: Chun Hua CHANG, Der-Chyang YEH, Kuang-Wei CHENG, Yuan-Hung LIU, Shang-Yun HOU, Wen-Chih CHIOU, Shin-Puu JENG
  • Patent number: 9660016
    Abstract: A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hua Chang, Der-Chyang Yeh, Kuang-Wei Cheng, Yuan-Hung Liu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
  • Publication number: 20170062392
    Abstract: Three dimensional integrated circuit structures and manufacturing methods of the same are disclosed. The three dimensional integrated circuit structure includes a first chip and a second chip. The first chip is bonded to the second chip at a bonding interface. A through via of the first chip and a bonding pad of the second chip are electrically connected, and a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface.
    Type: Application
    Filed: August 31, 2015
    Publication date: March 2, 2017
    Inventors: Kuang-Wei Cheng, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 9583465
    Abstract: Three dimensional integrated circuit structures and manufacturing methods of the same are disclosed. The three dimensional integrated circuit structure includes a first chip and a second chip. The first chip is bonded to the second chip at a bonding interface. A through via of the first chip and a bonding pad of the second chip are electrically connected, and a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuang-Wei Cheng, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 9565042
    Abstract: An ultra-low power transmitter applied in multi-channel frequency shift keying (FSK) communication is provided. The transmitter includes a fixed-frequency generation device, a low-frequency frequency synthesizer, and an injection locking device. The fixed-frequency generation device provides a reference frequency to the low-frequency frequency synthesizer. The frequency synthesizer divides the reference frequency with corresponding divisors for generating a plurality of divided frequency signals. Then, the divided frequency signals are injected into the injection locking device. The injection locking device will lock at the average frequency of previously mentioned divided frequencies. Wherein, the injection locking device filters the high frequency noise, which is produced by the frequency synthesizer, at the time of the injection locking. The ultra-low power transmitter obtains a high-frequency transmitted signal by using the frequency-locked signal.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: February 7, 2017
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Kuang-Wei Cheng, Wen-Hao Ho, Sheng-Kai Chang
  • Patent number: 9479115
    Abstract: A duplexer, applying in a cable modem, comprises a first mixer, a band-pass filter and a second mixer, in order to filter MoCA interference signal of downstream signals, a series of steps are carried out, which comprising up-conversion, filtering lower and lower frequency. The duplexer use a synthesizer to provide the local oscillator source to the first mixer and the second mixer according to the channel scan signals and use a channel scan controller to provide the channel scan signal of the local oscillator source to the synthesizer.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: October 25, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chun-Fa Liao, Kuang-Wei Cheng
  • Publication number: 20160191282
    Abstract: An ultra-low power transmitter applied in multi-channel frequency shift keying (FSK) communication is provided. The transmitter includes a fixed-frequency generation device, a low-frequency frequency synthesizer, and an injection locking device. The fixed-frequency generation device provides a reference frequency to the low-frequency frequency synthesizer. The frequency synthesizer divides the reference frequency with corresponding divisors for generating a plurality of divided frequency signals. Then, the divided frequency signals are injected into the injection locking device. The injection locking device will lock at the average frequency of previously mentioned divided frequencies. Wherein, the injection locking device filters the high frequency noise, which is produced by the frequency synthesizer, at the time of the injection locking. The ultra-low power transmitter obtains a high-frequency transmitted signal by using the frequency-locked signal.
    Type: Application
    Filed: December 30, 2015
    Publication date: June 30, 2016
    Inventors: Kuang-Wei CHENG, Wen-Hao HO, Sheng-Kai CHANG
  • Patent number: 9231596
    Abstract: A method and an apparatus for a duty-cycled injection locked oscillator is provided for frequency shift keyed (FSK) signal transmissions. The oscillator includes a resonance LC tank and a first switching device. The first switching device is coupled to the resonance LC tank and injects an initial current pulse with a predetermined pulse magnitude into the resonance LC tank. The initial current pulse also fixes an initial phase of the duty-cycled injection locked free-running oscillator in response to the predetermined magnitude of the initial current pulse to enable fast settling of injection locking and high data rate operation of the duty-cycled injection locked oscillator. The oscillator also includes a second switching device, such as a differential pair of switching devices. The second switching device is coupled to the LC resonance tank for injecting a gated periodic reference signal having a duty cycle modified to reduce power of the reference signal by approximately seventy-five per cent.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: January 5, 2016
    Assignee: Agency for Science, Technology and Research
    Inventors: Zhiming Chen, Kuang-Wei Cheng, Yuanjin Zheng, Minkyu Je
  • Publication number: 20150037960
    Abstract: A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor.
    Type: Application
    Filed: October 15, 2014
    Publication date: February 5, 2015
    Inventors: Chun Hua CHANG, Der-Chyang YEH, Kuang-Wei CHENG, Yuan-Hung LIU, Shang-Yun HOU, Wen-Chih CHIOU, Shin-Puu JENG
  • Publication number: 20150036554
    Abstract: A duplexer, applying in a cable modem, comprises a first mixer, a band-pass filter and a second mixer, in order to filter MoCA interference signal of downstream signals, a series of steps are carried out, which comprising up-conversion, filtering lower and lower frequency. The duplexer use a synthesizer to provide the local oscillator source to the first mixer and the second mixer according to the channel scan signals and use a channel scan controller to provide the channel scan signal of the local oscillator source to the synthesizer.
    Type: Application
    Filed: April 21, 2014
    Publication date: February 5, 2015
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHUN-FA LIAO, KUANG-WEI CHENG
  • Patent number: 8878338
    Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hua Chang, Der-Chyang Yeh, Kuang-Wei Cheng, Yuan-Hung Liu, Shang-Yun Hou, Wen-Chih Chiou, Shin-Puu Jeng
  • Publication number: 20140104010
    Abstract: A method and an apparatus for a duty-cycled injection locked oscillator is provided for frequency shift keyed (FSK) signal transmissions. The oscillator includes a resonance LC tank and a first switching device. The first switching device is coupled to the resonance LC tank and injects an initial current pulse with a predetermined pulse magnitude into the resonance LC tank. The initial current pulse also fixes an initial phase of the duty-cycled injection locked free-running oscillator in response to the predetermined magnitude of the initial current pulse to enable fast settling of injection locking and high data rate operation of the duty-cycled injection locked oscillator. The oscillator also includes a second switching device, such as a differential pair of switching devices. The second switching device is coupled to the LC resonance tank for injecting a gated periodic reference signal having a duty cycle modified to reduce power of the reference signal by approximately seventy-five per cent.
    Type: Application
    Filed: March 28, 2011
    Publication date: April 17, 2014
    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Zhiming Chen, Kuang-Wei Cheng, Yuanjin Zheng, Minkyu Je
  • Patent number: 8691706
    Abstract: System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Fang Wen Tsai, Kuang-Wei Cheng, Jiann Sheng Chang, Yi Chou Lai, Jiung Wu
  • Patent number: 8626110
    Abstract: A circuit arrangement is provided. The circuit arrangement includes a first input terminal and a second input terminal, a first transistor and a second transistor coupled to each other and to the first input terminal and the second input terminal, each of the first transistor and the second transistor having a first controlled terminal, a second controlled terminal and a control terminal, an input matching circuit coupled to the first input terminal, the second input terminal, the first transistor and the second transistor, a first resistive element coupled between the control terminal and the second controlled terminal of the first transistor, a second resistive element coupled between the control terminal and the second controlled terminal of the second transistor, and an output terminal coupled to the second controlled terminals of the first transistor and the second transistor.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: January 7, 2014
    Assignee: Agency for Science, Technology and Research
    Inventors: Kuang-Wei Cheng, Minkyu Je
  • Publication number: 20130329773
    Abstract: According to embodiments of the present invention, a receiver is provided. The receiver includes an envelope detector configured to generate a waveform corresponding to an envelope of a signal received by the receiver, a carrier recovery circuit configured to generate a carrier signal based on the waveform, wherein the carrier signal has a frequency corresponding to a center frequency of the received signal, and a template generator configured to generate a local template signal based on the waveform, the local template signal including a plurality of pulses. According to further embodiments of the present invention, a method of controlling a receiver is also provided.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 12, 2013
    Inventors: Kuang-Wei Cheng, Zhiming Chen, Yuanjin Zheng, Rui-Feng Xue, Minkyu Je
  • Publication number: 20130320493
    Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. A through via is formed in the interposer, and a capacitor is formed between a lower level metallization layer and a higher level metallization layer. The capacitor may be, for example, a planar capacitor with dual capacitor dielectric layers.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hua CHANG, Der-Chyang YEH, Kuang-Wei CHENG, Yuan-Hung LIU, Shang-Yun HOU, Wen-Chih CHIOU, Shin-Puu JENG
  • Publication number: 20130183831
    Abstract: System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.
    Type: Application
    Filed: January 12, 2012
    Publication date: July 18, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Fang Wen Tsai, Kuang-Wei Cheng, Jiann Sheng Chang, Yi Chou Lai, Jiung Wu
  • Publication number: 20130049839
    Abstract: According to embodiments of the present invention, a circuit arrangement is provided.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 28, 2013
    Inventors: Kuang-Wei CHENG, Minkyu JE
  • Publication number: 20120249250
    Abstract: According to embodiments of the present invention, a quadrature voltage controlled oscillator is provided.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 4, 2012
    Inventors: Kuang-Wei Cheng, Minkyu Je