Patents by Inventor Kuang-Wei Chiang

Kuang-Wei Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and mechanisms for inserting metal fill data
    Patent number: 8024677
    Abstract: A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record based on one or more rules, wherein the metal fill data represents a consolidation of actual metal fill. A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record, the metal fill data representing a virtual metal fill having a configuration that is different from a configuration of actual metal fill.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: September 20, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Terrence A Lenahan, Kuang-wei Chiang
  • METHODS AND MECHANISMS FOR INSERTING METAL FILL DATA
    Publication number: 20100235800
    Abstract: A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record based on one or more rules, wherein the metal fill data represents a consolidation of actual metal fill. A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record, the metal fill data representing a virtual metal fill having a configuration that is different from a configuration of actual metal fill.
    Type: Application
    Filed: May 24, 2010
    Publication date: September 16, 2010
    Inventors: Terrence A. Lenahan, Kuang-Wei Chiang, Jue Wang
  • Methods and mechanisms for inserting metal fill data
    Patent number: 7725859
    Abstract: A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record based on one or more rules, wherein the metal fill data represents a consolidation of actual metal fill. A method for implementing virtual metal fill includes obtaining a layout record for a circuit design, and inserting metal fill data into the layout record, the metal fill data representing a virtual metal fill having a configuration that is different from a configuration of actual metal fill.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: May 25, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Terrence A. Lenahan, Kuang-Wei Chiang, Jue Wang
  • Methods and mechanisms for implementing virtual metal fill
    Patent number: 7448010
    Abstract: A method for implementing virtual metal fill includes inserting metal fill data into a layout record based on one or more rules, extracting capacitance from the layout record to create a capacitance network, and reducing the capacitance network.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: November 4, 2008
    Assignee: Cadence Design Systems, Inc.
    Inventors: Terrence A. Lenahan, Kuang-Wei Chiang
  • Method of compressing data for use in performing VLSI mask layout verification
    Patent number: 5613102
    Abstract: A method of compressing data used in integrated circuit (IC) layout verifications includes the steps of identifying each circuit component from each layer of the IC chip; sorting each circuit component in an established order; identifying predetermined parameters for each component; determining the difference in value of the parameters for each pair of components in successive order; and storing the difference values for each pair of components.
    Type: Grant
    Filed: October 19, 1995
    Date of Patent: March 18, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: Kuang-Wei Chiang, Chi-Yuan Lo, Doowan Paik, Shun-Lin Su