Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Abstract: Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a stack, active structures connecting structures and isolation layers. The stack is disposed on the substrate. The active structures penetrate through the stack in sub-array regions thereof. A plurality of memory cells are defined by cross points of gate electrodes in the stack and the active structures. The connecting structures penetrate through the stack between the sub-array regions. Each connecting structure includes a first portion, a second portion and a third portion. The first portion is formed as an outermost layer of the connecting structure and formed of polysilicon. The second portion is disposed in a space defined by the first portion and formed of amorphous silicon. The third portion is disposed on the second portion and formed of amorphous silicon. The isolation layers are disposed between sidewalls of the stack and the connecting structures.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a conductive pillar having a sidewall and a multi-layer isolation structure on the sidewall of the conductive pillar. The multi-layer isolation structure includes a first isolation layer and a second isolation layer. The first isolation layer is between the conductive pillar and the second isolation layer. The first isolation layer includes protrusions extending toward the second isolation layer. A density of the first isolation layer is different from that of the second isolation layer.

Abstract: A semiconductor device includes a peripheral circuit region, a substrate on the peripheral circuit region, and an array region on the substrate. The peripheral circuit region has complementary metal-oxide-semiconductor components. The substrate includes an N-type doped poly silicon layer on the peripheral circuit region, an oxide layer on the N-type doped poly silicon layer, and a conductive layer on the oxide layer. The array region includes gate structures and insulating layers alternately stacked on the conductive layer. A bottommost gate structure and the conductive layer together serve as ground select lines of the semiconductor device, and a ratio of a thickness of the conductive layer to a thickness of each of the gate structures is about 3 to 4. The array region further includes a vertical channel structure penetrating the gate structures and the insulating layers and extending into the N-type doped poly silicon layer.

Abstract: A semiconductor device includes a peripheral circuit region, a substrate on the peripheral circuit region, and an array region on the substrate. The peripheral circuit region includes a plurality of complementary metal-oxide-semiconductor components. The substrate includes an N-type doped poly silicon layer on the peripheral circuit region, an insulating layer on the N-type doped poly silicon layer; and a P-type doped poly silicon layer on the insulating layer. The array region includes a plurality of gate structures and a plurality of oxide layers alternately stacked on the P-type doped poly silicon layer, wherein a bottommost gate structure of the gate structures and the P-type doped poly silicon layer together serve as a plurality ground select lines of the semiconductor device. The array region further includes a vertical channel structure penetrating the gate structures and the oxide layers and extending into the N-type doped poly silicon layer.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor are provided. The semiconductor structure includes a channel pillar, a dielectric layer formed on the channel pillar, a via formed in the dielectric layer and electrically connected to the channel pillar, and a spacer formed between the dielectric layer and the via.

Abstract: Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a source line structure. The source line structure includes a composite material formed in a trench. The composite material includes an oxide portion and a metal portion.

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a source line structure. The source line structure includes a composite material formed in a trench. The composite material includes an oxide portion and a metal portion.

Abstract: A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.

Abstract: A semiconductor device includes a substrate, a stacked structure disposed on the substrate, and dummy memory string structures. The stacked structure includes alternately stacked insulating layers and conductive layers. The dummy memory string structures disposed in a staircase region of the semiconductor device penetrate the stacked structure along a first direction. The staircase region includes a body portion including a first region and a second region adjacent to the first region. In the first region, an amount of conductive layers corresponding to the dummy memory string structures is between 1 and 10; in the second region, an amount of conductive layers corresponding to the dummy memory string structures is greater than 10. An area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second area under an identical unit area in a top view.

Abstract: A semiconductor device includes a substrate, a stacked structure disposed on the substrate, and dummy memory string structures. The stacked structure includes alternately stacked insulating layers and conductive layers. The dummy memory string structures disposed in a staircase region of the semiconductor device penetrate the stacked structure along a first direction. The staircase region includes a body portion including a first region and a second region adjacent to the first region. In the first region, an amount of conductive layers corresponding to the dummy memory string structures is between 1 and 10; in the second region, an amount of conductive layers corresponding to the dummy memory string structures is greater than 10. An area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second area under an identical unit area in a top view.

Abstract: A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.

Abstract: A semiconductor structure includes a substrate, at least one first conductive structure, at least one second conductive structure, at least one first memory structure, and at least one second memory structure. The substrate has an array region and a dummy region. The first conductive structure is disposed on the array region. The second conductive structure is disposed on the dummy region. The first memory structure is disposed on the first conductive structure. The first memory structure includes a first channel layer, and the first channel layer is in contact with the first conductive structure. The second memory structure is disposed on the second conductive structure. The second memory structure includes a second channel layer, and the second channel layer is isolated from the second conductive structure.

Abstract: The semiconductor structure includes a semiconductor device, a first metallization layer on the semiconductor device, a second metallization layer on the first metallization layer, and a third dielectric layer between the first metallization layer and the second metallization layer. The first metallization layer includes a first dielectric layer and a first metal layer disposed in the first dielectric layer, wherein the first metal layer has a first thickness, and the first metal layer comprises copper. The third dielectric layer has a second thickness, and a ratio of the second thickness of the third dielectric layer to the first thickness of the first metal layer is ranged from about 3 to about 20.

Abstract: The semiconductor structure includes a semiconductor device, a first metallization layer on the semiconductor device, a second metallization layer on the first metallization layer, and a third dielectric layer between the first metallization layer and the second metallization layer. The first metallization layer includes a first dielectric layer and a first metal layer disposed in the first dielectric layer, wherein the first metal layer has a first thickness, and the first metal layer comprises copper. The third dielectric layer has a second thickness, and a ratio of the second thickness of the third dielectric layer to the first thickness of the first metal layer is ranged from about 3 to about 20.

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.

Abstract: Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid inter-metal dielectric cracking and damage to the integrated circuit. The via is defined as a large open area in the inter-metal dielectric layer between an isolated conductive bottom substrate layer and a conductive top layer. Methods of manufacturing semiconductor devices with a large via are also provided.